EVAL-AD7763EBZ Analog Devices Inc, EVAL-AD7763EBZ Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD7763EBZ
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7763EBZ

• Lead Free Status / Rohs Status: Supplier Unconfirmed

AD7763
READING DATA USING THE I
The AD7763 has the capability of operating using an I
interface. The interface is functional only for the output of
stereo data and does not apply to writing to control registers,
programming coefficients for the digital filter, or the reading of
any information contained in the AD7763 onboard registers.
All of these operations must be undertaken using the normal
serial interface.
The I
shown in Table 9 are used as the output pins for the SCK (serial
clock), SD (serial data), and WS (word select) signals for the I
interface.
Table 9.
SPI Pins
FSO
SDO
SCO
To enable the I
Share Pins SH[2:0] of both AD7763 devices that use the I
interface are set to 001. The Address Pins ADR[2:0] of the two
devices must also be set to 000 and 001, respectively.
The WS and SCK signals that are used for the interface can be
taken from either AD7763 device. Note that the device that is
assigned Address 000 is defined as the left channel, and its data
is output on the SD line when WS is logic low.
The WS and SCK signals can be taken from the appropriate
pins on either of the AD7763 devices using the I
The SD pins of both devices must be connected together, as
shown in Figure 27.
Data is clocked out on the SD line in accordance with Figure 28.
Because Device A is assigned Address 000, it is defined as the
left channel. The 32-bit conversion result from the left channel
is clocked out when WS is logic low, with the MSB being clocked
out first. Each 32-bit result consists of 24 data bits in twos
complement format, followed by eight status bits, as shown in
the following bit map.
D7
DVALID
SCK A (O)
WS A (O)
2
SD (O)
S interface operates using two AD7763 devices. The pins
D6
OVR
2
S interface, the I
D5
UFILTER
RIGHT CHANNEL
(WORD n – 1)
DEVICE B
THREE-
STATE
D4
LPWR
I
WS
SD
SCK
2
S Signals
2
D23
S pin is set to logic high. The
D3
FILTER_OK
2
S INTERFACE
D22
D21
D2
ADR0
LEFT CHANNEL
2
S interface.
DEVICE A
(WORD n)
Figure 28. Timing Diagram for I
D1
0
2
S
2
S
ST2
D0
Three-
State
Rev. 0 | Page 18 of 32
2
S
ST1
THREE-
STATE
SH[2:0]
Conversion results from Device B, assigned Address 001, are
clocked out on the SD line when WS is logic high. The SD line
goes into three-state on the falling edge of the 32nd SCK after
the falling edge of WS (left channel data) and also on the falling
edge of the 32nd SCK after the rising edge of WS (right channel
data). This permits swapping of the SD bus between the left and
right channel devices without contention.
In decimate × 32 mode the I
when CDIV = 0 and SCR = 1. The interface operates for all
combinations of SCR and CDIV in all other modes of
decimation.
The DRDY pulse still operates as in the normal serial SPI-type
interface, pulsing low immediately prior to the falling edge of
WS but having no meaning in the I
MCLK
ADDRESS
ADDRESS
2
DEVICE
DEVICE
S Interface
D23
000
001
Figure 27. Two AD7763 Devices Operating Using the I
001
D22
1
1
D21
ADR[2:0]
I
SH[2:0]
SH[2:0]
I
ADR[2:0]
RIGHT CHANNEL
2
2
S
S
RIGHT CHANNEL
(WORD n + 1)
LEFT CHANNEL
DEVICE B
AD7763
AD7763
MCLK
MCLK
(000)
(001)
A
B
2
S interface is operational only
SCO
SDO
SDO
ST2
FSO
2
S interface specification.
ST1
THREE-
STATE
WS
SCK
SD
2
LEFT CHANNEL
S Interface
(WORD n + 2)
I
DEVICE A
2
S INTERFACE
3-WIRE