S2065A Applied Micro Circuits Corporation, S2065A Datasheet - Page 6

• Manufacturer Part Number: S2065A
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2065A

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

TRANSMITTER DESCRIPTION
The transmitter section of the S2065 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Four channels are
provided with a variety of options regarding input
clocking and loopback. The transmitters can operate
in the range of 770 MHz to 1.3 GHz, 10 or 20 times
the reference clock frequency. The transmitter func-
tions are shown schematically in Figure 4.
Data Input
The S2065 has been designed to simplify the parallel
interface data transfer and provide the utmost in flex-
ibility regarding clocking of parallel data. Prior, or less
sophisticated, implementations of this function have
either forced the user to synchronize transmit data to
the reference clock or to provide the output clock as a
reference to the PLL, resulting in increased jitter at
the serial interface. The S2065 incorporates a unique
input structure, which enables the user to provide a
“clean” reference source for the PLL and to accept a
separate external clock which is used exclusively to
reliably clock data into the device.
The S2065 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock.
6
S2065
Table 1. Input Modes
Note that internal synchronization of FIFOs is performed upon de-assertion of RESET.
C
H
A
N
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0
1
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Data is input to each channel of the S2065 nominally
as a 10-bit wide word. This consists of 8-bits of user
data, KGEN, and SOF. An input FIFO and a clock
input, TCLKx, are provided for each channel of the
S2065. The device can operate in two different
modes. In CHANNEL LOCK mode all four bytes of
the input data are clocked into their respective FIFOs
using a common clock. The S2065 can be configured
to use either the TCLKA (TCLK MODE) input or the
REFCLK input (REFCLK MODE). In NORMAL mode,
each byte of data is clocked into its FIFO with the
TCLKx provided with each byte. A TTL clock (TCLKO)
at the parallel data rate is provided by the S2065 for
use by upstream circuitry. The TCLKO is derived from
the transmit VCO. Table 1 provides a summary of the
input modes for the S2065.
Operation in the TCLK MODE makes it easier for
users to meet the relatively narrow setup and hold
time window required by the parallel 10-bit interface.
The TCLK signal is used to clock the data into an
internal holding register and the S2065 synchronizes
its internal data flow to ensure stable operation. The
TCLK is not used as a reference to the VCO. This
facilitates the provision of a clean reference clock
resulting in minimum jitter on the serial output. The
TCLK must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship.
Adjustment of internal timing of the S2065 is per-
formed during reset. Once synchronized, the S2065
can tolerate up to 3ns of phase drift between TCLK
and REFCLK.
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October 13, 2000 / Revision G
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