S2065A Applied Micro Circuits Corporation, S2065A Datasheet
S2065A
Specifications of S2065A
Related parts for S2065A
S2065A Summary of contents
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DEVICE SPECIFICATION QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O FEATURES • Broad operating rate range (770 MHz - 1.3 GHz) - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - ...
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S2065 Figure 2. Typical Backplane Application MAC (ASIC) MAC ATM (ASIC) Fibre S2065 Channel Ethernet MAC etc. (ASIC) MAC (ASIC) MAC (ASIC) MAC ATM (ASIC) Fibre S2065 Channel Ethernet MAC etc. (ASIC) MAC (ASIC) 2 QUAD SERIAL BACKPLANE DEVICE WITH ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 3. S2065 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO DINA[0:7] 10 SOFA, KGENA TCLKA DINB[0:7] 10 SOFB, KGENB TCLKB DINC[0:7] 10 SOFC, KGENC TCLKC DIND[0:7] 10 SOFD, KGEND TCLKD ERRA DOUTA[0:7] ...
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S2065 Figure 4. Transmitter Block Diagram RATE REFCLK CLKSEL CH_LOCK TMODE 8 DINA[0:7] FIFO SOFA (input) KGENA TCLKA 8 DINB[0:7] FIFO (input) SOFB KGENB TCLKB 8 DINC[0:7] FIFO (input) SOFC KGENC 0 ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 5. Receiver Block Diagram RATE CMODE REFCLK EOFA KFLAGA FIFO (output) ERRA 8 DOUTA[0:7] 2 RCAP/N EOFB KFLAGB FIFO (output) ERRB 8 DOUTB[0:7] 2 RCBP/N EOFC KFLAGC FIFO (output) ERRC 8 DOUTC[0:7] ...
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S2065 TRANSMITTER DESCRIPTION The transmitter section of the S2065 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Four channels are provided with a variety of options regarding input clocking and loopback. ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O The following figures illustrate the broad range of transmit data clocking options supported by the S2065. Figure 6 demonstrates the flexibility afforded by the S2065. A low jitter reference is provided directly to ...
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S2065 A special input is provided to simplify the generation of the K28.5 character. An SOFx input is provided for each channel. When SOF is asserted, the K28.5 character is generated regardless of the data on the parallel input. The ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 3. Data to 8B/10B Alphabetic Representation Table 4. Transmitter Control Signals (Normal Mode, CH_LOCK = ...
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S2065 Frequency Synthesizer (PLL) The S2065 synthesizes a serial transmit clock from the reference signal provided. The S2065 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock inputs. Reliable locking of the ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O RECEIVER DESCRIPTION Each receiver channel is designed to implement a Serial Backplane receiver function through the physi- cal layer. A block diagram showing the basic func- tion is provided in Figure 5. Whenever ...
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S2065 Reference Clock Input The reference clock must be provided from a low jitter clock source. The frequency of the received data stream (divided-by-10 or 20) must be within 200 ppm of the reference clock to ensure reliable locking of ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Loss of Channel Lock will be reported as indicated in Figure 9 and Table 1-0-1 on the ERR, EOF, and KFLAG signals, respectively. This is during the “No Sync” state. ...
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S2065 Figure 9. Channel Locking Synchronization Timing (Internal) RESYNC A (Internal) RESYNC B (Internal) RESYNC C (Internal) RESYNC D (internal) deskewed RESYNC A (internal) deskewed RESYNC B (internal) deskewed RESYNC C (internal) deskewed RESYNC D (internal) CHANNEL LOCK A,B,C,D ERRA ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O 8B/10B Decoding After performing serial-to-parallel conversion, the S2065 provides 8B/10B decoding of the data. The received 10-bit codeword is decoded to recover the original 8-bit data. The decoder also checks for er- rors ...
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S2065 Table 8. Error and Status Reporting ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O OTHER OPERATING MODES Operating Frequency Range The S2065 is designed to operate at serial baud rates of 770 MHz to 1.3 GHz (616 Mbit/sec to 1000 Mbit/sec user data rate). The part is ...
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S2065 Table 9. Transmitter Input Signals Assignment and Description ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 9. Transmitter Input Signals Assignment and Description (Continued ...
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S2065 Table 10. Transmitter Output Signals Assignment and Description ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 11. Mode Control Signals Assignment and Description ...
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S2065 Table 12. Receiver Output Signal Pin Assignment and Description ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 12. Receiver Output Signal Pin Assignment and Description (Continued ...
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S2065 Table 13. Receiver Input Signal Pin Assignment and Description ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 14. Receiver Control Signals Pin Assignment and Description ...
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S2065 Figure 11. S2065 Pinout (Bottom View ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 12. S2065 Pinout (Top View ...
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S2065 Figure 13. 208 TBGA Package Thermal Management Device S2065 28 QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O ja 17.7˚C/W 3.5˚C/W jc October 13, 2000 / Revision G ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 14. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 0) REFCLK DINx[0:7], SOFx, KGENx SERIAL DATA OUT Table 16. S2065 Transmitter Timing (Normal or Channel Lock Mode, TMODE = 0) P ...
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S2065 Figure 16. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Table 18. S2065 Receiver Timing (Full Clock Mode, CMODE = ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 18. TCLKO Timing REFCLK TCLKO Table 20. S2065 Transmitter (TCLKO Timing Note: Measurements ...
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S2065 Table 21. Absolute Maximum Ratings ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 24. Serial Data Timing, Transmit Outputs ...
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S2065 Table 26. DC Characteristics ...
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QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O OUTPUT LOAD The S2065 serial outputs require a resistive load to set the output current. The recommended resistor value is 4 ground. This value can be varied to adjust drive current, ...
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S2065 Figure 25. Loop Filter Capacitor Connections 36 QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O 270 CAP1 22 nf CAP2 270 S2065 October 13, 2000 / Revision G ...
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... C Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...