ADM6996LAAT1NP Infineon Technologies, ADM6996LAAT1NP Datasheet - Page 35
ADM6996LAAT1NP
Manufacturer Part Number
ADM6996LAAT1NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.ADM6996LAAT1NP.pdf
(69 pages)
Specifications of ADM6996LAAT1NP
Lead Free Status / Rohs Status
Not Compliant
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Step4: Set Port5 MII Port as Tag Port and set PVID=2.
{Coding:Write Register 09
Step5: Group Port0, 1, 2, 3, 5 as VLAN 1.
{Coding: Write Register 14
Step6: Group Port4, 5 as VLAN 2.
{Coding: Write Register 15
How MAC Clone Operation:
•
ADM6996L/LX LAN traffic to LAN/CPU only. Traffic to another LAN port will be
untag packet. Traffic to CPU is Tag packet with VID=1. CPU can check VID to
distinguish LAN traffic or WAN traffic.
•
ADM6996L/LX WAN traffic to CPU only. Traffic to CPU is Tag packet with VID=2.
CPU can check VID to distinguish LAN traffic or WAN traffic.
•
ADM6996L/LX CPU Packet to LAN port must add VID=1 in VLAN field.
ADM6996L/LX check VID to distinguish LAN traffic or WAN traffic. LAN output
packet is Untag.
•
ADM6996L/LX CPU Packet to WAN port must add VID=2 in VLAN filed.
ADM6996L/LX check VID to distinguish LAN traffic or WAN traffic. WAN output
packet is Untag.
•
ADM6996L/LX will check VLAN mapping setting first then check learning table.
User does not worry LAN/WAN traffic mix up.
Bit 10: Half Duplex Back Pressure enable. 1/enable, 0/disable.
Configuration Register 3
ConfigReg_3
Miscellaneous Configuration Register 3
Field
CD
Data Sheet
LAN to LAN/CPU Traffic.
WAN to CPU Traffic.
CPU to LAN Packet.
CPU to WAN Packet.
ADM6996L/LX learning sequence
Bits
15
H
H
H
as 881F
as 0155
as 0180
Type
rw
H
H
H
. Port5 MII port as Tag, PVID=2.}
. VLAN1 cover Port0, 1, 2, 3, 5.}
. VLAN2 cover Port4, 5.}
Description
Excessive Collision Drop
0
1
B
B
D, Disable
E, Enable
Offset
12
35
H
Registers DescriptionEEPROM Content
Rev. 1.13, 2005-11-22
ADM6996L/LX
Data Sheet
Reset Value
3600
H
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