ADM6996LAAT1NP Infineon Technologies, ADM6996LAAT1NP Datasheet
ADM6996LAAT1NP
Specifications of ADM6996LAAT1NP
Related parts for ADM6996LAAT1NP
ADM6996LAAT1NP Summary of contents
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... ITAC ® ® ® QUAT , QuadFALC , SCOUT ® ® 10BaseV , 10BaseVX are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft ® Corporation, Linux of Linus Torvalds, Visio Incorporated. Data Sheet ® ® ® , ASP , DigiTape , DuSLIC ® ...
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Table of Contents 1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.15.5 Inter-Packet Gap (IPG ...
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List of Figures Figure 1 ADM6996L/LX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Product Overview 1.1 Overview The ADM6996L/ high performance, low cost, highly integration (Controller, PHY and Memory) five-port 10/100 Mbps TX/FX plus one 10/100 MAC port Ethernet switch controller with all ports supporting 10/100 Mbps Full/Half duplex. The ...
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Applications ADM6996L/LX in 128-pin PQFP: SOHO 5-port switch 5-port switch + Router with MII CPU interface. 1.4 Block Diagram Figure 1 below shows a simple block diagram of the ADM6996L/LX internal blocks. Addr Table 2K Entry Packet Buffer Figure ...
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Interface Description This chapter describes the interface for the ADM6996L/LX. 2.1 Pin Diagram 103 DUPCOL4 104 GNDO 105 VCC3O 106 DUPCOL3 107 DUPCOL2 (BPEN) 108 DUPCOL1 (PHYAS1) 109 DUPCOL0 (RECANEN) 110 VCCIK 111 GNDIK 112 RC 113 XI 114 ...
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Twisted Pair Interface Table 1 Twisted Pair Interface Pin or Ball Name No. 126 RXP0 11 RXP1 24 RXP2 37 RXP3 41 RXP4 127 RXN0 12 RXN1 25 RXN2 38 RXN3 40 RXN4 123 TXP0 8 TXP1 21 TXP2 ...
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Table 2 6th Port (MII) Interfaces (cont’d) Pin or Ball Name No. 61 TXD[1] SettingP5GPSI 59 TXD3 60 TXD2 62 P4FX 66 XEN SettingPHYAS0 74 RXD0 100 RXD1 101 RXD2 102 RXD3 73 RXDV 68 RXER 78 COL 77 CRS ...
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Table 2 6th Port (MII) Interfaces (cont’d) Pin or Ball Name No. 91 DHALFP5 90 LNKFP5 TNP5 2.2.3 LED Interface Table 3 LED Interface Pin or Ball Name No. 98 LNKACT0 97 LNKACT1 96 LNKACT2 95 LNKACT3 ...
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Table 3 LED Interface (cont’d) Pin or Ball Name No. 107 DUPCOL2 SettingBPEN 108 DUPCOL1 SettingPHYAS1 109 DUPCOL0 SettingANEN 50 LDSPD0 51 LDSPD1 54 LDSPD2 55 LDSPD3 58 LDSPD4 2.2.4 EEPROM/Management Interface Data Sheet Pin Buffer Function Type Type O ...
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Table 4 EEPROM/Management Interface Pin or Ball Name No. 84 EDO 80 EECS 81 EECK SettingXOVEN 79 EDI SettingLEDMOD E 2.2.5 Power/Ground, 48 pins Table 5 Power/Ground, 48 pins Pin or Ball Name No. 3, 10, 16, 23, GNDA 29, ...
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Table 5 Power/Ground, 48 pins (cont’d) Pin or Ball Name No. 46, 57, 70, GNDO 87, 99, 104 56, 71, 88, VCC3O 105 69 GND 2.2.6 MISC Table 6 MISC Pin or Ball Name No. 85 CKO25M 117 Control 120 ...
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Function Description 3.1 Functional Descriptions The ADM6996L/LX integrates five 100Base-X physical sub-layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, five complete 10Base-T modules port 10/100 switch controller and one 10/100 MII/GPSI MAC and memory into a single ...
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A/D Converter A high performance A/D converter with a 125 MHz sampling rate converts signals received on the RXP/RXN pins to 6 bits data streams. It possess an auto-gain-control capability that will further improve receive performance especially under long ...
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Receive Errors The RXER signal is used to communicate receiver error conditions. While the receiver state of holding RXDV asserted, the RXER will be asserted for each code word that does not map to a valid ...
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Transmit Drivers The ADM6996L/LX 100Base-TX transmission driver implements MLT-3 translation and wave-shaping functions. The rise/fall time of the output signal is closely controlled to conform to the target range as specified in the ANSI TP-PMD standard. 3.5.2 Twisted-Pair Receiver ...
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Smart Squelch The smart squelch circuit is responsible for determining when valid data is present on the differential receive. The ADM6996L/LX implements an intelligent receive squelch on the RXP/RXN differential inputs to ensure that impulse noise on the receive ...
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Auto Negotiation The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide ...
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If the SA was not found in the Address Table (a new address), the ADM6996L/LX waits until the end of the packet (non-error packet) and updates the Address Table. If the SA was found in the Address Table, then ...
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ADM6996L/LX to prevent the back pressure function causing HUB partitioned under heavy traffic environment and reducing the packet loss rate to increase the whole system performance. 3.15.8 Full Duplex Flow Control When full duplex port run out ...
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Meanwhile port-base VLAN could be enabled according to the PVID value (user define 4bits to map 16 groups written at register 13 to register 22) of the configuration content of each port. ADM6996L/LX also supports 16 802.1Q VLAN groups. In ...
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LED-High Link/Act Figure 3 LED Display Data Sheet Single Color R? 510 Dual Color Mode R? 510 D? LED D? LED 25 ADM6996L/LX Function Description Mode D? VCC LED Speed Rev. 1.13, 2005-11-22 Data Sheet ...
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Registers Description 4.1 EEPROM Content Table 9 Registers Address SpaceRegisters Address Space Module Base Address EEPROM 00 H Table 10 Registers Overview Register Short Name Register Long Name SigReg Signature Register ConfigReg_0 Configuration Register 0 ResReg_0 Reserved Register 0 ...
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Table 11 Register Access Types Mode Symbol Description HW read/write rw Register is used as input for the HW read r Register is written by HW (register between input and output -> one cycle delay) Read only ro Register is ...
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SigReg Signature Register Field Bits Type Signature 15:0 ro Note: ADM6996L/LX will check register 0 value before read all EEPROM content. If this value not match with 0x4154h then other values in EEPROM will be useless. ADM6996L/LX will use internal ...
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Field Bits Type PPE DUP 3 rw OPS Reserved Register 0 Register reserved for future use ResReg_0 Reserved Register 0 Field ...
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Configuration Register 1 Used to configure the chip ConfigReg_1 Configuration Register 1 Field Bits Type Res 14 IPG 6 rw Res 5:0 ro Reserved Register 1 Reserved for future use ResReg_1 Reserved Register ...
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Field Bits Type Res 15:0 ro VLAN Priority Map Register Sets the VLAN priorities VLAN_Map_P VLAN priority Map Register Field Bits Type V7 15: 13: 11 5:4 rw ...
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Field Bits Type T7 15: 13: 11 1:0 rw Note: Value are for priority queues Q3~Q0 respectively. The Weight ...
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Field Bits Type Res 6 ro Res Res 1:0 rw Note: Broadcast storm initial time interval = 50ms. The max. packet number = 7490 in 100Base, 749 in 10Base ...
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Field Bits Type Res 15:8 ro Res 7 MAC 4 rw Res 3:0 ro Note: Below is an example of a VLAN Tag and a MAC application for Bit4 and Bit5. Below is an old router ...
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Step4: Set Port5 MII Port as Tag Port and set PVID=2. {Coding:Write Register 09 as 881F H Step5: Group Port0 VLAN 1. {Coding: Write Register 14 as 0155 H Step6: Group Port4 VLAN ...
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Field Bits Type Res 14 rw Res 13:12 rw Res 11 rw Res 10:9 rw ML5 8 rw ML4 7 rw ML3 6 rw Res 5 rw ML2 4 rw Res 3 rw ML1 2 rw Res 1 rw ML0 ...
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Field Bits Type VM2 4 rw Res 3 ro VM1 2 rw Res 1 ro VM0 0 rw Note: 16 VLAN Group: See Register 2C Reserved Register 3 ResReg_3 Reserved Register 3 Field Bits Type Res 15:0 rw Reserved Register ...
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Field Bits Type Res 15:0 rw Reserved Register 6 ResReg_6 Reserved Register 6 Field Bits Type Res 15:0 rw Reserved Register 7 ResReg_7 Reserved Register 7 Field Bits Type Res 15:0 rw Configuration Register 4 ConfigReg_4 Configuration Register 4 Data ...
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Field Bits Type Res 15 7:0 rw Configuration Register 5 ConfigReg_5 Configuration Register 5 Field Bits Type Res 15 7:0 rw Configuration Register 6 ConfigReg_6 Configuration Register 6 Field Bits Type Res 15:8 ro Data Sheet ...
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Field Bits Type P2 7:0 rw Configuration Register 7 ConfigReg_7 Configuration Register 7 Field Bits Type P4 15 7:0 rw Configuration Register 8 ConfigReg_8 Configuration Register Field Bits Type CR0 15 rw CR1 14 rw Data Sheet Registers ...
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Field Bits Type CR2 13 rw CR3 12 rw Res 10 7:0 rw Note: Bit[10:8]: VLAN Tag shift register. ADM6996L/LX will select 4 bit form total 12 bit VID as VLAN group reference. Bit[15:12]: IEEE ...
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Field Bits Type Res 15:0 rw PHY Restart PH_Restart PHY Restart Field Bits Type PR 15:0 rw Configuration Register 9 ConfigReg_ Miscellaneous Configuration Register 9 Field Bits Type Res 15: Res 11 rw Res 10 rw ...
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Field Bits Type Res 8 rw Res 7 rw RCL 6 rw MAC 5 rw Res 4:0 rw Bandwidth Control Register BWCon_0 Bandwidth Control Register 0 Field Bits Type RC3 15 rw P3T 14:12 rw RC2 11 ...
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Table 17 Note:Reference Table 000 001 010 256K 512K 1M Bandwidth Control Register 1 BWCon_1 Bandwidth Control Register 1 Field Bits Type Res 15:8 ro RC5 7 rw P5T 6:4 rw RC4 3 rw P4T 2:0 rw Table 18 Note:Reference ...
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Field Bits Type Res 15:9 ro BW5 8 rw BW4 7 rw BW3 6 rw Res 5 rw BW2 4 rw Res 3 rw BW1 2 rw Res 1 rw BW0 0 rw Data Sheet Registers DescriptionEEPROM Content Description Reserved ...
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Serial Register Map Table 19 Registers Address SpaceRegisters Address Space Module Base Address Serial 00 H Table 20 Registers Overview Register Short Name Register Long Name ChipID Chip Identifier Register PortStat_0 Port Status Register 0 PortStat_1 Port Status Register ...
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Table 21 Register Access Types (cont’d) Mode Symbol Description HW Interrupt low, ilmk Differentiate the input signal (low- mask clearing >high) register cleared with written mask Interrupt enable ien Enables the interrupt source for register interrupt generation latch_on_reset lor rw ...
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Field Bits Type FP4 31 ro DP4 30 ro SP4 29 ro LP4 28 ro FP3 27 ro DP3 26 ro SP3 25 ro LP3 24 ro Res 23:20 ro FP2 19 ro DP2 18 ro SP2 17 ro LP2 ...
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Field Bits Type FP1 11 ro DP1 10 ro SP1 9 ro LP1 8 ro Res 7:4 ro FP0 3 ro DP0 2 ro SP0 1 ro LP0 0 ro Port Status Register 1 PortStat_1 Port Status Register 1 Field ...
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Field Bits Type SP5 2:1 ro LP5 0 ro Cable Broken Status Register CabStat Cable Broken Status Field Bits Type Res 31:24 ro CB4 23 ro CL4 22:21 ro CB3 20 ro CL3 19:18 ro Res 17:15 ro CB2 14 ...
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Field Bits Type Res 31:18 ro OR5 17 ro OR4 16 ro OR3 15 ro Res 14 ro OR2 13 ro Res 12 ro OR1 11 ro Res 10 ro OR0 9 ro OF5 8 ro OF4 7 ro OF3 ...
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Field Bits Type Res 14 ro OB2 13 ro Res 12 ro OB1 11 ro Res 10 ro OB0 9 ro OF5 8 ro OF4 7 ro OF3 6 ro Res 5 ro OF2 4 ro Res 3 ro OF1 ...
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Field Bits Type OF2 4 ro Res 3 ro OF1 2 ro Res 1 ro OF0 0 ro 4.3 VLAN Packet Table 23 VLAN Packet Tag Protocol TD 8100 Tag Control Information TCI Byte 12~13 Byte14~15 Note: ADM6996L/LX will check ...
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Table 25 RESETL & EEPROM content relationship RESETL CS 0 High Impedance Rising edge 01 Output (30ms) 1 (after 30ms) Input Keep at least 30ms after RESETL from 01. ADM6996L/LX will read data from EEPROM. After RESETL if CPU update ...
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Figure 4 ADM6996L/LX Serial Chip’s Internal Counter or EEPROM Access Timing Preamble: At least 32 continuous 1 Start bits) B Opcode bits, Only supports a read command) B Table select Counter EEPROM ...
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Preamble: At least 32 continuous 1 Start bits) B Opcode bits, Reset command) B Device Address: Chip physical address as PHYAS[1:0]. Reset_type: Reset the counter by port number or by counter index 1 = Clear dedicate ...
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Electrical Specification 5.1 TX/FX Interface 5.1.1 TP Interface Transformer requirement: • TX/RX rate 1:1 • TX/RX central tap connect together to VCCA2 Note: Users can change the TX/RX pin for easy layout but do not change polarity. The ADM6996L/LX ...
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TXP TXN ADM6996L RXP RXN Figure 7 Fx Interface Layout 5.2 DC Characteristics 5.2.1 Absolute Maximum Rating Table 26 Absolute Maximum Rating Parameter Power Supply TX line driver PLL voltage Digital core voltage Input Voltage Output Voltage Storage Temperature Power ...
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Recommended Operating Conditions Table 27 Recommended Operating Conditions Parameter Power Supply TX line driver PLL voltage Digital core voltage Input Voltage Power consumption Junction Operating Temperature 5.2.3 DC Electrical Characteristics for 3.3 V Operation Under Vcc=3.0 V~3.6 V, Tj= ...
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RST* All Configuration Pins Figure 8 Power On Reset Table 29 Power On Reset Symbol Parameter TRST RST Low Period TCONF Start of Idle Pulse Width 5.3.2 EEPROM Interface Timing Describes the EEPROM timing values 0us EECS EESK tEWDD EEDO ...
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Table 30 EEPROM Interface Timing (cont’d) Parameter EEDI to EESK Rising Setup Time EEDI to EESK Rising Hold Time EESK Falling to EEDO Output Delay Time 5.3.3 10Base-Tx MII Input Timing 10Base-Tx Input timing conditions 0us EECS EESK tEWDD EEDO ...
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MII_TXCLK MII_TXEN MII TXD Figure 11 10Base-TX MII Output Timing Table 32 10Base-TX MII Output Timing Parameter MII_TXCLK Period MII_TXCLK Low Period MII_TXCLK High Period MII_TXD, MII_TXEN to MII_TXCLK Rising Output Delay 5.3.5 100Base-Tx MII Input Timing 100Base Tx ...
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Table 33 100Base-TX MII Input Timing Parameter MII_RXCLK Period MII_RXCLK Low Period MII_RXCLK High Period MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising hold 5.3.6 100Base-TX MII Output Timing 100Base-TX MII Output timing ...
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GPSI_RXCLK GPSI_RXD GPSI_CRS/COL Figure 14 GPSI(7-wire) Input Timing Table 35 GPSI (7-wire) Input Timing Parameter GPSI_RXCLK Period GPSI_RXCLK Low Period GPSI_RXCLK High Period GPSI_RXD, GPSI_CRS /COL to GPSI_RXCLK Rising Setup Time GPSI_RXD, GPSI_ CRS/COL to GPSI_RXCLK Rising Hold Time ...
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Table 36 GPSI (7-wire) Output Timing Parameter GPSI_TXCLK Period GPSI_TXCLK Low Period GPSI_ T XCLK High Period GPSI_ T XCLK Rising to GPSI_TXEN/GPSI_TXD Output Delay Data Sheet Symbol Values Min. Typ. tCK 100 tCKL 40 tCKH 40 tOD 50 65 ...
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Packaging This chapter describes the ADM6996L/LX’s packaging. 6.1 128 Pin PQFP Outside Dimension ADM6996L/LX packaging Figure 16 128-pin LQFP Chip Package Data Sheet 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12 ADM6996L/LX Data Sheet ...
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TerminologyTerminology A B Data Sheet 67 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...
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... Published by Infineon Technologies AG ...
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Data Sheet 69 ADM6996L/LX Data Sheet Rev. 1.13, 2005-11-22 ...