CLC5957PCASM/NOPB National Semiconductor, CLC5957PCASM/NOPB Datasheet - Page 2

• Manufacturer Part Number: CLC5957PCASM/NOPB
• Manufacturer: National Semiconductor

Specifications of CLC5957PCASM/NOPB

• Lead Free Status / Rohs Status: Compliant

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A
A
ENCODE
ENCODE
V
D0–D11
GND
+AV
+DV
NC
DAV
OUTLEV
Pin Configuration
Pin Descriptions
IN
IN
CM
CC
CC
Name
Pin
20, 23–26, 35, 36, 47, 48
1–4, 8, 11, 12, 15, 19,
5–7, 16–18, 22
37, 38, 46
30–34,
13, 14
39–45
9, 10
Pin
No.
21
29
27
28
01502901
Differential input with a common mode voltage of +2.4V. The ADC
full scale input is 1.024 V
signals.
Differential clock where ENCODE initiates a new data conversion
cycle on each rising edge. Logic for these inputs are a 50% duty
cycle universal differential signal (
internally biased to V
Internal common mode voltage reference. Nominally +2.4V. Can be
used for the input common mode voltage. This voltage is derived
from an internal bandgap reference. V
driving any external load. Failure to buffer this signal can cause
errors in the internal bias currents.
Digital data outputs are CMOS and TTL compatible. D0 is the LSB
and D11 is the MSB. MSB is inverted. Output coding is two’s
complement. Current limited to source/sink 2.5mA typical.
Circuit ground.
+5V power supply for the analog section. Bypass to ground with a
0.1 µF capacitor.
+5V power supply for the digital section. Bypass to ground with a
0.1 µF capacitor.
No connect. May be left open or grounded.
Data Valid Clock. Data is valid on rising edge. Current limited to
source/sink 5mA typical.
Output Logic 3.3V or 2.5V option. Open = 3.3V, GND = 2.5V.
2
Ordering Information
CLC5957MTD
CLC5957MTDX
CLC5957PCASM
CC
/2 with a termination impedance of 2.5k .
PP
Description
on each of the complimentary input
>
200mV). The clock input is
48-Pin TSSOP
48-Pin TSSOP (Taped
Reel)
Evaluation Board
CM
should be buffered when