CLC5957PCASM/NOPB National Semiconductor, CLC5957PCASM/NOPB Datasheet - Page 15

• Manufacturer Part Number: CLC5957PCASM/NOPB
• Manufacturer: National Semiconductor

Specifications of CLC5957PCASM/NOPB

• Lead Free Status / Rohs Status: Compliant

CLC5957 Applications
Digital Outputs and Level Select
Figure 6 depicts the digital output buffer and bias used in the
CLC5957. Although each of the twelve output bits uses a
controlled current buffer to limit supply transients, it is rec-
ommended that parasitic loading of the outputs is minimized.
Because these output transients are harmonically related to
the analog input signal, excessive loading will degrade ADC
performance at some frequencies.
The logic high level is slaved to the internal 2.4V reference.
The OUTLEV control pin selects either a 3.3V or 2.5V logic
high level. An internal pull up resistor selects the 3.3V level
as the default when the OUTLEV pin is left open. Grounding
the OUTLEV pin selects the 2.5V logic high level.
To ease user interface to subsequent digital circuitry, the
CLC5957 has a data valid clock output (DAV). In order to
match delays over IC processing variables, this digital output
also uses the same output buffer as the data bits. The DAV
clock output is simply a delayed version of the ENCODE
input clock. Since the ADC output data change is slaved to
the falling edge of the ENCODE clock, the rising DAV clock
edge occurs near the center of the data valid window (or
eye) regardless of the sampling frequency.
Minimum Conversion Rate
This ADC is optimized for high-speed operation. The internal
bipolar track and hold circuits will cause droop errors at low
sample rates. The point at which these errors cause a deg-
radation of performance is listed on the specification page as
the minimum conversion rate. If a lower sample rate is
desired, the ADC should be clocked at a higher rate, and the
output data should be decimated. For example, to obtain a
10MSPS output, the ADC should be clocked at 20MHZ, and
every other output sample should be used. No significant
FIGURE 6. CLC5957 Digital Outputs
(Continued)
015029F7
15
power savings occurs at lower sample rates, since most of
the power is used in analog circuits rather than digital cir-
cuits.
CLC5957 Evaluation Board
Description
The Evaluation board for the CLC5957 allows for easy test
and evaluation of the product. The part may be ordered with
all components loaded and tested. The order number is the
CLC5957PCASM. The user supplies an analog input signal,
encode signal and power to the board and is able to take
latched 12-bit digital data out of the board.
ENCODE Input (ENC)
The ENCODE input is an SMA connector with a termination
of 50 . The encode signal is converted to an AC coupled,
differential clock signal centered between V
The user should supply a sinusoidal or square wave signal of
cycle can vary from 50% if the minimum clock pulse width
times are observed. A low jitter source will be required for
IF-sampled analog input signals to maintain best perfor-
mance.
CLC5957 Clock Option
The CLC5957 evaluation board is configured for use with an
optional crystal clock oscillator source. The component Y1
may be loaded with a ’Full-sized’, HCMOS type, crystal
oscillator.
Analog Input (AIN)
The analog input is an SMA connector with a 50
tion. The signal is converted from single to differential by a
transformer with a 5 to 260MHz bandwidth and approxi-
mately one dB loss. Full scale is approximately 11dBm or
2.2V
input signal be low jitter, low noise and low distortion to allow
for proper test and evaluation of the CLC5957.
Supply voltages (J1 pins 31 A&B and 32 A&B)
The CLC5957PCASM is powered from a single 5V supply
connected from the referenced pins on the Eurocard con-
nector. The recommended supplies are low noise linear
supplies.
Digital Outputs (J1 pins 7B (MSB, D11) through 18B
(LSB) and 20B (Data Valid))
The digital outputs are provided on the Eurocard connector.
The outputs are buffered by 5V CMOS latches with 50
series output resistors. The rising edge of Data Valid may be
used to clock the output data into data collection cards or
logic analyzers. The board has a location for the HP
01650-63203 termination adapter for HP 16500 logic analyz-
ers to simplify connection to the analyzer.
>
200mV
PP
. It is recommended that the source for the analog
PP
and
<
4 V
PP
with a 50% duty cycle. The duty
CC
and ground.
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