CLC5957PCASM/NOPB National Semiconductor, CLC5957PCASM/NOPB Datasheet - Page 14

• Manufacturer Part Number: CLC5957PCASM/NOPB
• Manufacturer: National Semiconductor

Specifications of CLC5957PCASM/NOPB

• Lead Free Status / Rohs Status: Compliant

www.national.com
CLC5957 Applications
Analog Inputs and Bias
Figure 1 depicts the analog input and bias scheme. Each of
the differential analog inputs are internally biased to a nomi-
nal voltage of 2.40V DC through a 500
impedance buffer. This enables a simple interface to a
broadband RF transformer with a center-tapped output wind-
ing that is decoupled to the analog ground. If the application
requires the inputs to be DC coupled, the V
used to establish the proper common-mode input voltage for
the ADC. The V
internal bandgap source that is very accurate and stable.
The V
When the V
mirror is disabled and the total current is reduced to less than
10mA. Figure 2 depicts how this function can be used. The
diode is necessary to prevent the logic gate from altering the
ADC bias value.
ENCODE Clock Inputs
The CLC5957’s differential input clock scheme is compatible
with all commonly used clock sources. Although small differ-
ential and single-ended signals are adequate, for best aper-
ture jitter performance a low noise differential clock with a
high slew rate is preferred. As depicted in Figure 3 , both
ENCODE clock inputs are internally biased to V
a pair of 5k
any common-mode voltage between the supply and ground.
CM
output may also be used to power down the ADC.
FIGURE 2. Power Shutdown Scheme
FIGURE 1. CLC5957 Bias Scheme
CM
resistors. The clock input buffer operates with
CM
pin is pulled above 3.5V, the internal bias
voltage reference is generated from an
CM
resistor to a low
015029F2
output can be
CC
/2 through
015029F1
14
The internal bias resistors simplify the clock interface to
another center-tapped transformer as depicted in Figure 4 . A
low
amplitude (1 − 4V
face.
Figure 5 shows the clock interface scheme for square wave
clock sources.
FIGURE 5. TTL, 3V CMOS or 5V CMOS Clock Scheme
FIGURE 4. Transformer Coupled Clock Scheme
phase
FIGURE 3. CLC5957 ENCODE Clock Inputs
noise,
PP
) can drive the ADC through this inter-
RF
synthesizer
015029F5
of
015029F3
015029F4
moderate