SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 21

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

Architecture Overview
AMD Geode™ SC1200/SC1201 Processor Data Book
Note:
GX_BASE+8414h-8417h
GX_BASE+8418h-841Bh
GX_BASE+841Ch-841Fh
31:18
15:12
31:10
10:8
10:0
31:2
Bit
6:4
3:0
9:0
11
17
16
11
7
1
0
Refer to the SDRAM manufacturer’s specification for more information on component banks.
Description
RSVD (Reserved). Write as 0.
RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command
to two different component banks within the same module bank. The memory controller does not perform back-to-back Acti-
vate commands to two different component banks without a READ or WRITE command between them. Hence, this field
should be written as 001.
RSVD (Reserved). Write as 0.
DPL (Data-in to PRE Command Period, tDPL). Minimum number of SDRAM clocks from the time the last write datum is
sampled till the bank is precharged:
000: Reserved
001: 1 CLK
RSVD (Reserved). Leave unchanged. Always returns a 101h.
RSVD (Reserved). Write as 0.
TE (Test Enable TEST[3:0]).
0: TEST[3:0] are driven low (normal operation).
1: TEST[3:0] pins are used to output test information
TECTL (Test Enable Shared Control Pins).
0: RASB#, CASB#, CKEB, WEB# (normal operation).
1: RASB#, CASB#, CKEB, WEB# are used to output test information
SEL (Select). This field is used for debug purposes only and should be left at zero for normal operation.
RSVD (Reserved). Write as 0.
GBADD (Graphics Base Address). This field indicates the graphics memory base address, which is programmable on 512
KB boundaries. This field corresponds to address bits [29:19].
Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.
RSVD (Reserved). Write as 0.
DRADD (Dirty RAM Address). This field is the address index that is used to access the Dirty RAM with the MC_DR_ACC
register. This field does not auto increment.
RSVD (Reserved). Write as 0.
D (Dirty Bit). This bit is read/write accessible.
V (Valid Bit). This bit is read/write accessible.
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers (Continued)
010: 2 CLK
011: 3 CLK
100: 4 CLK
101: 5 CLK
MC_GBASE_ADD (R/W)
MC_DR_ADD (R/W)
MC_DR_ACC (R/W)
110: 6 CLK
111: 7 CLK
32579B
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 0000000xh
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