AD5763CSUZ-REEL7 Analog Devices Inc, AD5763CSUZ-REEL7 Datasheet - Page 16

• Manufacturer Part Number: AD5763CSUZ-REEL7
• Description: DAC 16BIT DUAL 5V 2LSB 32-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5763CSUZ-REEL7

• Design Resources: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074)
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 45mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5763
THEORY OF OPERATION
The AD5763 is a dual, 16-bit, serial input, bipolar voltage
output DAC and operates from supply voltages of ±4.75 V to
±5.25 V. The part has a specified buffered output voltage of up
to ±4.311 V. Data is written to the AD5763 in a 24-bit word
format via a 3-wire serial interface. The device also offers an
SDO pin, which is available for daisy-chaining or readback.
The AD5763 incorporates a power-on reset circuit, which
ensures that the DAC registers power-up loaded with 0x0000.
The AD5763 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers, per channel
digital gain, and offset registers.
DAC ARCHITECTURE
The DAC architecture of the AD5763 consists of a 16-bit
current mode segmented R-2R ladder DAC. The simplified
circuit diagram for the DAC section is shown in Figure 25.
The four MSBs of the 16-bit data-word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one
of the 15 matched resistors to either AGNDx or IOUT. The
remaining 12 bits of the data-word drive Switch S0 to Switch
S11 of the 12-bit R-2R ladder network.
REFERENCE BUFFERS
The AD5763 operates with an external reference. The reference
inputs (REFA and REFB) have an input range up to 2.1 V. This
input voltage is then used to provide a buffered positive and
negative reference for the DAC cores. The positive reference
(V
The negative reference (V
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
V
REF
REFP
E15
2R
4 MSBs DECODED INTO
V
V
15 EQUAL SEGMENTS
) is given by
REFP
REFN
E14
2R
= 2V
= −2V
REF
E1
REF
Figure 25. DAC Ladder Structure
2R
R
S11
12-BIT, R-2R LADDER
2R
REFN
R
S10
) to the DAC cores is given by
2R
R
S0
2R
2R
AGNDx
IOUT
R/8
VOUTx
Rev. A | Page 16 of 28
SERIAL INTERFACE
The AD5763 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI™, MICROWIRE™, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits and 16
data bits as shown in Table 8. The timing diagram for this
operation is shown in Figure 2.
Upon power-up, the DAC registers are loaded with zero code
(0x0000) and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at this
time by asserting either LDAC or CLR . The corresponding output
voltage depends on the state of the BIN/ 2sCOMP pin. If BIN/
2sCOMP is tied to DGND, then the data coding is twos comple-
ment and the outputs update to 0 V. If the BIN/ 2sCOMP pin is
tied to DV
update to negative full-scale. To have the outputs power-up with
zero code loaded to the outputs, the CLR pin should be held low
during power-up.
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can only be
used if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used and SYNC must be taken high after
the final clock to latch the data. The first falling edge of SYNC
starts the write cycle. Exactly 24 falling clock edges must be
applied to SCLK before SYNC is brought high again. If SYNC is
brought high before the 24
written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, then the input data
is also invalid. The addressed input register is updated on the
rising edge of SYNC . For another serial transfer to take place,
SYNC must be brought low again. After the end of the serial
data transfer, data is automatically transferred from the input
shift register to the addressed register.
When the data has been transferred into the chosen register
of the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low.
CC
, then the data coding is offset binary and the outputs
th
falling SCLK edge, then the data