CS4351-DZZ Cirrus Logic Inc, CS4351-DZZ Datasheet - Page 24

• Manufacturer Part Number: CS4351-DZZ
• Description: IC DAC STER 112DB 192KHZ 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4351-DZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 354mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1152 - BOARD EVAL FOR CS4351 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24
6. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
6.1
6.2
6.2.1
6.2.2
Note:
Reserved
PART4
7
1
7
0
DIF2
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining Bits
(2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
Mode Control 1 - Register 02h
De-emphasis is only available in Single-Speed Mode
0
0
0
0
1
1
1
1
Digital Interface Format (DIF2:0) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in
De-Emphasis Control (DEM1:0) Bits 3-2
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
Function:
Selects the appropriate digital filter to maintain the stan-
dard 15 µs/50 µs digital de-emphasis filter response at
32, 44.1 or 48 kHz sample rates. (See
DIF1
PART3
DIF2
0
0
1
1
0
0
1
1
6
1
6
0
DIF0
0
1
0
1
0
1
0
1
PART2
DIF1
5
1
5
0
Left Justified, up to 24-bit data
I
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
2
S, up to 24-bit data
Table 7. Digital Interface Formats
PART1
DIF0
Figure
4
1
4
0
DESCRIPTION
11.)
Figures 5
.
PART0
DEM1
3
1
3
0
through 7.
-10dB
Gain
0dB
dB
Figure 11. De-Emphasis Curve
DEM0
REV2
2
2
0
-
3.183 kHz
T1=50 µs
F1
0
Format
(Default)
REV1
1
2
3
4
5
FM1
1
1
0
-
10.61 kHz
F2
FIGURE
T2 = 15 µs
Frequency
5
6
7
7
7
7
CS4351
REV0
DS566F1
FM0
0
0
0
-