LTC1428CS8-50#PBF Linear Technology, LTC1428CS8-50#PBF Datasheet - Page 7

IC DAC 8BIT SINK OUT 8-SOIC

LTC1428CS8-50#PBF

Manufacturer Part Number
LTC1428CS8-50#PBF
Description
IC DAC 8BIT SINK OUT 8-SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1428CS8-50#PBF

Number Of Bits
8
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
120µW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Channels
1
Resolution
8b
Interface Type
SERIAL 1,2,3 WIRE
Single Supply Voltage (typ)
3.3V
Dual Supply Voltage (typ)
Not RequiredV
Power Supply Requirement
Single
Output Type
Current
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
6.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Resolution (bits)
8bit
Input Channel Type
Serial
Supply Current
130µA
Digital Ic Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
0°C To +70°C
Msl
MSL 1 - Unlimited
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Settling Time
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1428CS8-50#PBFLTC1428CS8-50
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC1428CS8-50#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC1428CS8-50#PBFLTC1428CS8-50#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS
shifted in, a rising edge at CS transfers the data from the
input shift register into the DAC register. The DAC output
assumes the new value and the D
impedance state.
1-Wire Interface (Pulse Mode, Figure 4)
In 1-wire pulse mode, each rising edge at CLK increments
the upper six bits of the DAC register by one count. When
incremented beyond 11111100B, the counter rolls over
and sets the DAC to the minimum value (00000000B). In
this way, a single pulse applied to CLK increases the DAC
output by a single 4LSB step and 63 pulses decrease the
TYPICAL
I
OUT
= (B7 B6 B5 B4 B3 B2 B1 B0)I
V
0.1 F
CC
Figure 3. 3-Wire Mode; Serial Interface
(3-Wire Control by CS, CLK and D
V
0.1 F
D
FOR HALF-DUPLEX DATA TRANSFER
Figure 4. Pulse Mode: Increment Only
(1-Wire Control by CLK)
CC
IN
AND D
APPLICATION
OUT
SHDN
I
CLK
OUT
U
SHDN
CAN BE TIED TOGETHER
I
D
OUT
CLK
OUT
D
CS
IN
1
2
3
4
INFORMATION
1
2
3
4
I
V
SHDN
CLK
OUT
CC
V
V
U
I
V
Pulse Mode: Increment-Only (1-Wire Control by CLK) with Voltage Output
OUT
DD
SHDN
CLK
LTC1428-50
OUT
CC
LTC1428-50
= (I
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
V
OUT
V
OUT
OUT
OUT
D
GND
OUT
D
+ 1V, 2V V
)(R
CS
U
D
IN
GND
OUT
D
W
CS
FB
IN
pin returns to a high-
8
7
6
5
1428-50 F04
) + V
FULLSCALE
6
5
8
7
6
100k
BIAS
R
IN
FB
BIAS
1428-50 F03
)
V
LT1006
V
D
DD
10V
EE
OUT
7
4
U
/255
+
3
2
V
BIAS
SHDN
CLK
DAC output by one step. The last two LSBs are always zero
in pulse mode.
To configure the LTC1428-50 in 1-wire pulse mode, tie
both the CS and D
2-Wire Interface (Pulse Mode, Figure 5)
In 2-wire pulse mode, a logic high at UP/DN programs the
DAC register to increment and each rising edge at CLK
increments the upper six bits of the register by one count.
Similarly, a logic low at UP/DN programs the DAC register
to decrement and a rising edge at CLK decrements the
upper six bits of the register by one count. Each count in
2-wire mode changes the DAC output by a single 4LSB
step. The DAC register stops incrementing at 11111100B
and stops decrementing at 00000000B and will not roll
over in 2-wire pulse mode. The last two LSBs are always
zero in pulse mode.
To configure the LTC1428-50 in 2-wire pulse mode, tie CS
to V
power-up.
1
2
3
4
I
I
I
V
SHDN
CLK
OUT
OUT
OUT
CC
CC
LTC1428-50
and bring the UP/DN pin low at least once during
= (B7 B6 B5 B4 B3 B2 0 0)I
= (B7 B6 B5 B4 B3 B2 0 0)I
Figure 5. Pulse Mode; Increment/Decrement
(2-Wire Control by CLK and UP/DN)
D
V
0.1 F
GND
CC
OUT
D
CS
IN
6
5
8
7
1428-50 TA02
IN
UP/DN
SHDN
I
CLK
OUT
pins to V
V
D
CC
OUT
1
2
3
4
I
V
SHDN
CLK
OUT
CC
LTC1428-50
CC
.
D
GND
OUT
D
CS
IN
FULLSCALE
FULLSCALE
LTC1428-50
6
5
8
7
1428-50 F05
D
OUT
/255
/255
7

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