MAX5888AEGK+D Maxim Integrated Products, MAX5888AEGK+D Datasheet - Page 11

• Manufacturer Part Number: MAX5888AEGK+D
• Description: IC DAC 16BIT 3.3V 500MSPS 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5888AEGK+D

• Settling Time: 11ns
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 130mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

frequencies. Their differential characteristic supports
the transmission of high-speed data patterns without
the negative effects of electromagnetic interference
(EMI). All MAX5888 LVDS inputs feature on-chip termi-
nation with differential 100Ω resistors. See Figure 6 for
a simplified block diagram of the LVDS inputs.
A common-mode level of 1.25V and an 800mV differen-
tial input swing can be applied to these inputs.
Segment shuffling can improve the SFDR of the
MAX5888. The improvement is most pronounced at
higher output frequencies and amplitudes. Note that an
improvement in SFDR can only be achieved at the cost
of a slight increase in the DAC’s noise floor.
Pin SEL0 controls the segment-shuffling function. If
SEL0 is pulled low, the segment-shuffling function of
the DAC is disabled. SEL0 can also be left open,
because an internal pulldown resistor helps to deacti-
vate the segment-shuffling feature. To activate the
MAX5888 segment-shuffling function, SEL0 must be
pulled high.
The MAX5888 also features an active-high power-down
mode, which allows the user to cut the DAC’s digital
current consumption to less than 6µA and the analog
current consumption to less than 0.3mA. A single pin
(PD) is used to control the power-down mode (PD = 1)
or reactivate the DAC (PD = 0) after power-down.
Figure 5. Detailed Timing Relationship
Performance DAC with Differential LVDS Inputs
B0 TO B15
CLKP
CLKN
IOUT
N - 5
______________________________________________________________________________________
DIGITAL DATA IS LATCHED ON
THE RISING EDGE OF CLKP
t SETUP
Power-Down Operation (PD)
Segment Shuffling (SEL0)
3.3V, 16-Bit, 500Msps High Dynamic
N - 1
t HOLD
N - 4
OUTPUT DATA IS UPDATED ON
THE FALLING EDGE OF CLKP
t PD
N
N - 3
Enabling the power-down mode of the MAX5888 allows
the overall power consumption to be reduced to less
than 1mW. The MAX5888 requires 10ms to wake up
from power-down and enter a fully operational state.
The differential voltage existing between IOUTP and
IOUTN can also be converted to a single-ended volt-
age using a transformer (Figure 7) or a differential
amplifier configuration. Using a differential transformer
coupled output, in which the output power is limited to
0dBm, can optimize the dynamic performance.
However, make sure to pay close attention to the trans-
former core saturation characteristics when selecting a
transformer for the MAX5888. Transformer core satura-
tion can introduce strong 2nd-harmonic distortion,
especially at low output frequencies and high signal
Figure 6. Simplified LVDS-Compatible Input Structure
B0N–B15N
B0P–B15P
100Ω
Applications Information
N + 1
Differential Coupling Using a
N - 2
Wideband RF Transformer
t CH
CLOCK
t CL
D
D
N + 2
N - 1
Q
Q
TO DECODE
LOGIC
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