MAX5184BEEG+ Maxim Integrated Products, MAX5184BEEG+ Datasheet - Page 11

• Manufacturer Part Number: MAX5184BEEG+
• Description: IC DAC 10BIT DUAL 40MHZ 24-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5184BEEG+

• Settling Time: 25µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Resolution: 10 bit
• Interface Type: Parallel
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
Figure 4. Timing Diagram
D0–D9
OUT
CLK
THD
10-Bit, 40MHz, Current/Voltage-Output DACs
=
20 log
×
t
DS
______________________________________________________________________________________
⎛
⎜
⎜
⎝
(V
2
N - 1
2
Total Harmonic Distortion
+
V
3
2
V
+
1
Digital Feedthrough
V
t
CLK
4
2
N - 1
+
V )
Settling Time
5
2
Offset Error
Gain Error
⎞
⎟
⎟
⎠
N
where V
V
harmonics.
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion com-
ponent.
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5181. The differential
voltage across OUTP and OUTN is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
The low-distortion performance of two MAX5181/
MAX5184s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) archi-
tectures where two separate buses carry the I and Q
data. A QAM signal is both amplitude (AM) and phase
modulated, created by summing two independently
modulated carriers of identical frequency but different
phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5181/MAX5184 may be used to reconstruct the
analog I and Q components.
t
DH
5
are the amplitudes of the 2nd- through 5th-order
Differential to Single-Ended Conversion
1
is the fundamental amplitude, and V
N
t
CL
Spurious-Free Dynamic Range
N + 1
in a QAM Application
t
CH
I/Q Reconstruction
N + 1
2
through
11