CS4341A-KSZ Cirrus Logic Inc, CS4341A-KSZ Datasheet - Page 8

• Manufacturer Part Number: CS4341A-KSZ
• Description: IC DAC STER 24BIT 192KHZ 16SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341A-KSZ

• Package / Case: 16-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V or 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 125 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1633

3.3
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)
clocks. The LRCK, defined also as the input sample rate (F
MCLK according to specified ratios. The specified ratios of MCLK to LRCK for each Speed Mode, along
with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.
* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).
3.4
The device will accept audio samples in several digital interface formats. The desired format is selected
via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of
the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.
8
L R C K
S C L K
S D IN
Sample Rate
Sample Rate
Sample Rate
(kHz)
(kHz)
176.4
(kHz)
88.2
44.1
192
System Clocking
Digital Interface Format
64
96
32
48
M SB
-1 -2 -3 -4 -5
11.2896
12.2880
12.2880
11.2896
8.1920
8.1920
128x
256x
22.5792
24.5760
Table 3. Single-Speed Mode Standard Frequencies
Table 4. Double-Speed Mode Standard Frequencies
128x
Table 5. Quad-Speed Mode Standard Frequencies
+5 +4
L e ft C h a n n e l
+3 +2 +1
12.2880
16.9344
18.4320
12.2880
16.9344
18.4320
192x
384x
LSB
Figure 2. I
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
16.3840
22.5792
24.5760
16.3840
22.5792
24.5760
2
S Data
256x
512x
33.8688
36.8640
192x
s
), must be synchronously derived from the
M SB
-1 -2 -3 -4
24.5760
33.8688
36.8640
24.5760
33.8688
36.8640
384x
768x
+5 +4
R ig h t C h a n n e l
+3 +2 +1
45.1584
49.1520
256x*
32.7680
45.1584
49.1520
32.7680
45.1584
49.1520
LSB
1024x*
512x*
CS4341A
DS582F2