CS4341A-KSZ Cirrus Logic Inc, CS4341A-KSZ Datasheet - Page 18

IC DAC STER 24BIT 192KHZ 16SOIC

CS4341A-KSZ

Manufacturer Part Number
CS4341A-KSZ
Description
IC DAC STER 24BIT 192KHZ 16SOIC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4341A-KSZ

Package / Case
16-SOIC
Number Of Bits
24
Data Interface
Serial
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
90mW
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
3.3 V or 5 V
Operating Temperature Range
+ 70 C
Maximum Power Dissipation
125 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1633

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4341A-KSZ
Manufacturer:
CIRRUS
Quantity:
676
Part Number:
CS4341A-KSZ
Manufacturer:
CIRRUS
Quantity:
20 000
18
DIF2
5.2.2 DIGITAL INTERFACE FORMAT (DIF)
5.2.1 AUTO-MUTE (AMUTE)
5.2.3 DE-EMPHASIS CONTROL ( DEM[1:0] )
0
0
0
0
1
1
1
1
Function:
Function:
Function:
Default = 1
0 - Disabled
1 - Enabled
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and mut-
ing is done independently for each channel. The quiescent voltage on the output will be retained and
the Mute Control pin will go active during the mute period. The muting function is affected, similiar to
volume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address
02h) register.
Default = 000 - Format 0 (I
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 2-4.
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 5, requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates.
NOTE: De-emphasis is only available in Single-Speed Mode.
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
BIT 7
I
Identical to Format 1
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 1
2
S, up to 24-bit data
Table 6. Digital Interface Format
2
S, up to 24-bit data)
BIT 4-6
BIT 2-3
DESCRIPTION
Format
1
1
2
3
4
5
6
1
CS4341A
FIGURE
DS582F2
2
2
3
4
4
4
4
2

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