AD5446YRMZ Analog Devices Inc, AD5446YRMZ Datasheet - Page 7

• Manufacturer Part Number: AD5446YRMZ
• Description: IC DAC 14BIT MULTIPLYING 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5446YRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151)
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 50.5µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 14bit
• Sampling Rate: 2.7MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 400nA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5446EBZ - BOARD EVALUATION FOR AD5446
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
I
I
GND
SCLK
SDIN
SYNC
SDO
V
V
R
OUT
OUT
FB
DD
REF
1
2
Description
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground Pin.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to the rising edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low,
data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising
edge of SYNC.
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to data loaded to the shift register.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input.
DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.
SCLK
I
I
SDIN
OUT
OUT
GND
Figure 5. Pin Configuration
1
2
Rev. C | Page 7 of 28
1
2
3
4
5
(Not to Scale)
AD5444/
AD5446
TOP VIEW
10
9
8
7
6
R
V
V
SDO
SYNC
REF
DD
FB
AD5444/AD5446