AD5446YRMZ Analog Devices Inc, AD5446YRMZ Datasheet - Page 5

• Manufacturer Part Number: AD5446YRMZ
• Description: IC DAC 14BIT MULTIPLYING 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5446YRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151)
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 50.5µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 14bit
• Sampling Rate: 2.7MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 400nA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5446EBZ - BOARD EVALUATION FOR AD5446
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
Update Rate
1
SYNC
SCLK
SCLK
1
2
3
4
5
6
7
8
9
SDIN
Guaranteed by design and characterization; not subject to production test.
SDO
NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
REF
= 10 V, I
1
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications T
V
5.5 V
50
20
8
8
8
5
4.5
5
30
23
2.7
DD
t
SYNC
SCLK
4
SDIN
= 4.5 V to
DB15 (N)
t
8
t
5
t
t
6
4
V
5.5 V
50
20
8
8
8
5
4.5
5
30
30
2.7
DB15
DD
= 2.5 V to
t
5
t
6
t
2
Figure 3. Daisy-Chain Timing Diagram
Figure 2. Standalone Timing Diagram
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
t
2
t
1
t
Rev. C | Page 5 of 28
3
t
DD
1
DB0 (N)
Conditions/Comments
Maximum clock frequency.
SCLK cycle time.
SCLK high time.
SCLK low time.
SYNC falling edge to SCLK active edge setup time.
Data setup time.
Data hold time.
SYNC rising edge to SCLK active edge setup time
Minimum SYNC high time.
SCLK active edge to SDO valid.
Consists of cycle time, SYNC high time, data setup time and output
voltage settling time.
t
3
) and timed from a voltage level of (V
t
9
DB0
t
DB15 (N)
7
(N + 1)
DB15
MIN
to T
MAX
IL
, unless otherwise noted.
+ V
IH
AD5444/AD5446
)/2. V
DD
DB0 (N)
(N + 1)
DB0
= 2.5 V to 5.5 V,
t
7
t
8