CAT5419WI-50-T1 ON Semiconductor, CAT5419WI-50-T1 Datasheet - Page 7

• Manufacturer Part Number: CAT5419WI-50-T1
• Description: IC POT DPP 50K 64TAP 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5419WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Number Of Elements: 2
• # Of Taps: 64
• Resistance (max): 50KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE OPERATIONS
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of CAT5419. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The CAT5419
acknowledges once more and the Master generates
the STOP condition, at which time if a nonvolatile data
register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the CAT5419 initiates the
Figure 5. Slave Address Bits
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
BUS ACTIVITY :
SD LINE
MASTER
A
S
A
R
T
T
S
CAT5419
Fixed
SLAVE/DPP
ADDRESS
Variable
0
1
C
A
K
op code
0
INSTRUCTION
7
1
BYTE
Data Register
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the CAT5419 is still
busy with the write operation, no ACK will be returned.
If the CAT5419 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the WP
registers are protected and become read only.
Similarly, WP
non-volatile write to data registers, while WP
LOW after internal write cycle has started will have no
effect on any write operation. The CAT5419 will
accept both slave addresses and instructions, but the
data registers are protected from programming by the
device’s failure to send an acknowledge after data is
received.
Address
A3
Pot/WCR
Address
A2
A
C
K
¯¯¯ pin going LOW after Start will interrupt
DR1 WCR DATA
A1
A0
¯¯¯ pin is tied to LOW, the data
A
C
K
P
O
S
T
P
Doc. No. MD-2115 Rev. J
¯¯¯ pin going
CAT5419