CAT5419WI-50-T1 ON Semiconductor, CAT5419WI-50-T1 Datasheet - Page 6

• Manufacturer Part Number: CAT5419WI-50-T1
• Description: IC POT DPP 50K 64TAP 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5419WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Number Of Elements: 2
• # Of Taps: 64
• Resistance (max): 50KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CAT5419
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
(2) During a data transfer, the data line must remain
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5419 will be considered a slave device in all
applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5419 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
Figure 4. Acknowledge Timing
Doc. No. MD-2115 Rev. J
is not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
START
1
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of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the CAT5419 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
After the Master sends a START condition and the
slave address byte, the CAT5419 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
The CAT5419 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT5419 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT5419 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
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ACKNOWLEDGE
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Characteristics subject to change without notice
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