SST39WF1601-70-4C-Y1QE Microchip Technology, SST39WF1601-70-4C-Y1QE Datasheet - Page 9

• Manufacturer Part Number: SST39WF1601-70-4C-Y1QE
• Description: 1.65V To 1.95V 16Mbit Multi-Purpose Flash 48 WFBGA 4x6x0.8 Mm TRAY
• Manufacturer: Microchip Technology
• Series: -r

Specifications of SST39WF1601-70-4C-Y1QE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-WFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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©2011 Silicon Storage Technology, Inc.
Data Protection
Hardware Data Protection
Hardware Block Protection
Hardware Reset (RST#)
Software Data Protection (SDP)
The SST39WF1601/1602 provide both hardware and software features to protect nonvolatile data from
inadvertent writes.
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
The SST39WF1602 support top hardware block protection, which protects the top 32 KWord block of
the device. The SST39WF1601 support bottom hardware block protection, which protects the bottom
32 KWord block of the device. The Boot Block address ranges are described in Table 3. Program and
Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally
held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase opera-
tions on that block.
Table 3: Boot Block Address Ranges
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least T
no internal Program/Erase operation is in progress, a minimum period of T
is driven high before a valid Read can take place (see Figure 16).
The Erase or Program operation that has been interrupted needs to be reinitiated after the device
resumes normal operation mode to ensure data integrity.
The SST39WF1601/1602 provide the JEDEC approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled. See Table 6 for the specific software com-
mand codes. During SDP command sequence, invalid commands will abort the device to read mode
within T
sequence.
Product
Bottom Boot Block
Top Boot Block
DD
SST39WF1601
SST39WF1602
Power Up/Down Detection: The Write operation is inhibited when V
RC.
The contents of DQ
RP,
any in-progress operation will terminate and return to Read mode. When
15
-DQ
8
16 Mbit Multi-Purpose Flash Plus
can be V
9
IL
or V
SST39WF1601 / SST39WF1602
IH
, but no other value, during any SDP command
0F8000H-0FFFFFH
000000H-007FFFH
Address Range
DD
is less than 1.5V.
RHR
is required after RST#
DS-25014A
Data Sheet
T3.0 25014
04/11