PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 168

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K90 FAMILY
TABLE 11-10: PORTE FUNCTIONS
DS39957B-page 168
RE0/LCDBIAS1/
P2D
RE1/LCDBIAS2/
P2C
RE2/LCDBIAS3/
P2B
RE3/COM0/
P3C/CCP9/
REFO
RE4/COM1/
P3B/CCP8
RE5/COM2/
P1C/CCP7
RE6/COM3/
P1B/CCP6
Legend:
Note 1:
Pin Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
LCDBIAS1
LCDBIAS2
LCDBIAS3
Function
COM0
REFO
COM1
COM2
COM3
CCP9
CCP8
CCP7
CCP6
RE0
P2D
RE1
P2C
RE2
P2B
RE3
P3C
RE4
P3B
RE5
P1C
RE6
P1B
Setting
TRIS
—
—
0
1
0
0
1
0
0
1
x
0
0
1
x
0
0
1
x
0
1
x
0
0
1
0
1
x
0
0
1
0
1
x
0
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
Preliminary
LATE<0> data output.
PORTE<0> data input.
LCD module bias voltage input.
ECCP2 PWM Output D. May be configured for tri-state during
Enhanced PWM shutdown events.
LATE<1> data output.
PORTE<1> data input.
LCD module bias voltage input.
ECCP2 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
LATE<2> data output.
PORTE<2> data input.
LCD module bias voltage input.
ECCP2 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
LATE<3> data output.
PORTE<3> data input.
LCD Common 0 output; disables all other outputs.
ECCP3 PWM Output C. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP9 compare/PWM output. Takes priority over port data.
CCP9 capture input.
Reference output clock.
LATE<4> data output.
PORTE<4> data input.
LCD Common 1 output; disables all other outputs.
ECCP3 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP8 Compare/PWM output. Takes priority over port data.
CCP8 capture input.
LATE<5> data output.
PORTE<5> data input.
LCD Common 2 output; disables all other outputs.
ECCP1 PWM Output C. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP7 Compare/PWM output. Takes priority over port data.
CCP7 capture input.
LATE<6> data output.
PORTE<6> data input.
LCD Common 3 output; disables all other outputs.
ECCP1 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP6 Compare/PWM output. Takes priority over port data.
CCP9 capture input.
Description
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