MAX5432LETA+T Maxim Integrated Products, MAX5432LETA+T Datasheet - Page 8

• Manufacturer Part Number: MAX5432LETA+T
• Description: IC POT DGTL 32-TAP NV I2C 8-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5432LETA+T

• Taps: 32
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN Exposed Pad
• Resistance In Ohms: 50K
• Number Of Pots: Single
• Taps Per Pot: 32
• Resistance: 50 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire, I2C)
• Operating Supply Voltage: 5 V
• Supply Current: 0.002 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Description/function: 32-Tap, Nonvolatile, I2C, Linear, Digital Potentiometers, 50kohm Resistor Divider
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX5432LETA+T

32-Tap, Nonvolatile, I
Potentiometers
The MAX5432–MAX5435 contain a resistor array with
31 resistive elements. The MAX5432/MAX5434 provide
a total end-to-end resistance of 50kΩ, and the
MAX5433/MAX5435 provide an end-to-end resistance
of 100kΩ.
The MAX5432/MAX5433 allow access to the high, low,
and wiper terminals for a standard voltage-divider con-
figuration. Connect H, L, and W in any desired configu-
ration as long as their voltages fall between GND and
V
with H internally connected to the wiper.
A simple 2-wire I
the wiper among the 32 tap points. Eight data bits, an
address byte, and a control byte program the wiper
position. A nonvolatile memory stores and recalls the
wiper position in the nonvolatile memory upon power-up.
The nonvolatile memory is guaranteed for 200,000 wiper
store cycles and 50 years for wiper data retention.
The MAX5432–MAX5435 feature an internal, nonvolatile
EEPROM that returns the wiper to its previously stored
position at power-up. The shift register decodes the
control and address bits, routing the data to the proper
memory registers. Write data to the volatile memory
register to immediately update the wiper position, or
write data to the nonvolatile register for storage. Writing
to the nonvolatile register takes a minimum of 12ms.
The volatile register retains data as long as the device
is enabled and powered. Removing power clears the
volatile register. The nonvolatile register retains data
even after power is removed. Upon power-up, the
8
DD
_______________________________________________________________________________________
TDFN
. The MAX5434/MAX5435 are variable resistors
EP
1
2
3
4
5
6
7
8
PIN
THIN SOT23
2
C-compatible serial interface moves
—
—
—
4
2
3
1
6
5
Detailed Description
NAME
GND
SDA
SCL
V
A0
EP
W
H
DD
L
Digital Interface
High Terminal
I
Ground
I
Power-Supply Input. Bypass with a 0.1µF capacitor from V
Address Input. Sets the I
Low Terminal
Wiper Terminal
Exposed Pad. Internally connected to GND.
2
2
C-Compatible Interface Data Input
C-Compatible Interface Clock Input
2
C, Linear, Digital
2
C address. Connect to V
power-on reset circuitry and internal oscillator control
the transfer of data from the nonvolatile register to the
volatile register.
The MAX5432–MAX5435 operate as a slave that sends
and receives data through an I
patible 2-wire interface. The interface uses a serial data
access (SDA) line and a serial clock line (SCL) to
achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX5432–MAX5435, and generates the SCL clock that
synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain out-
put. SDA requires a pullup resistor, typically 4.7kΩ.
SCL only operates as an input. SCL requires a pullup
resistor (4.7kΩ typ) if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the
MAX5432–MAX5435 7-bit slave address plus the 8th bit
(Figure 4), 1 command byte (Figure 7) and 1 data byte,
and finally a STOP (P) condition (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
SMBus is a trademark of Intel Corporation.
FUNCTION
DD
or GND. Do not leave A0 floating.
DD
Start and Stop Conditions
to GND.
Pin Description
2
C- and SMBus™-com-
Serial Addressing