AD7890ARZ-10 Analog Devices Inc, AD7890ARZ-10 Datasheet - Page 4

• Manufacturer Part Number: AD7890ARZ-10
• Description: IC DAS 12BIT 8CH 24-SOIC
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS)r

Specifications of AD7890ARZ-10

• Resolution (bits): 12 b
• Data Interface: Serial
• Sampling Rate (per Second): 117k
• Voltage Supply Source: Single Supply
• Voltage - Supply: ±10V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Current: 10mA
• Digital Ic Case Style: MSOP
• No. Of Pins: 24
• Sampling Rate: 117kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Parameter
f
t
t
tr
tf
t
t
Self-Clocking Mode
External-Clocking Mode
NOTES
1
2
3
4
5
6
AD7890
Sample tested at –25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figures 8 to 11.
The AD7890 is production tested with f
Specified using 10% and 90% points on waveform of interest.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
CLKIN
CLK IN LO
CLK IN HI
CONVERT
CST
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the tim ing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
4
4
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
19A
20
21
22
23
5
5
6
5
5
6
6
3
Limit at T
(A, B, S Versions)
100
2.5
0.3 × t
0 3 × t
25
25
5.9
100
t
25
t
t
20
40
50
0
t
0
20
10
20
20
40
50
50
35
20
50
90
20
10
15
40
CLK IN HI
CLK IN HI
CLK IN LO
CLK IN
CLK IN
CLK IN
CLK IN
+ 50
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
+ 50
1, 2
MIN
, T
(V
connected to SHA IN.)
MAX
DD
TO OUTPUT
= 5 V
PIN
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
µs max
ns min
ns max
ns max
ns nom
ns nom
ns max
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
50pF
5%, AGND = DGND = 0 V, REF IN = 2.5 V, f
Conditions/Comments
Master Clock Frequency. For Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
Digital Output Rise Time. Typically 10 ns
Digital Output Fall Time. Typically 10 ns
Conversion Time
CONVST Pulsewidth
RFS Low to SCLK Falling Edge
RFS Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Delay
SCLK Rising Edge to RFS Delay
Bus Relinquish Time after Rising Edge of SCLK
TFS Low to SCLK Falling Edge
Data Valid to TFS Falling Edge Setup Time (A2 Address Bit)
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS to SCLK Falling Edge Hold Time
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS to SCLK Falling Edge Hold Time
1.6mA
200 A
+2.1V
CLK IN
= 2.5 MHz external, MUX OUT