AD7890ARZ-10 Analog Devices Inc, AD7890ARZ-10 Datasheet - Page 12

• Manufacturer Part Number: AD7890ARZ-10
• Description: IC DAS 12BIT 8CH 24-SOIC
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS)r

Specifications of AD7890ARZ-10

• Resolution (bits): 12 b
• Data Interface: Serial
• Sampling Rate (per Second): 117k
• Voltage Supply Source: Single Supply
• Voltage - Supply: ±10V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Current: 10mA
• Digital Ic Case Style: MSOP
• No. Of Pins: 24
• Sampling Rate: 117kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7890
In the Self-Clocking Mode, the AD7890 indicates when conver-
sion is complete by bringing the RFS line low and initiating a
serial data transfer. In the external clocking mode, there is no
indication of when conversion is complete. In many applica-
tions, this will not be a problem as the data can be read from the
part during conversion or after conversion. However, applications
that seek to achieve optimum performance from the AD7890
will have to ensure that the data read does not occur during
conversion or during 500 ns prior to the rising edge of CONVST.
This can be achieved in either of two ways. The first is to ensure
in software that the read operation is not initiated until 5.9 µs
after the rising edge of CONVST. This will only be possible if
the software knows when the CONVST command is issued. The
second scheme would be to use the CONVST signal as both the
conversion start signal and an interrupt signal. The simplest way
to do this would be to generate a square wave signal for CONVST
with high and low times of 5.9 µs (see Figure 6). Conversion is
initiated on the rising edge of CONVST. The falling edge of
CONVST occurs 5.9 µs later and can be used as either an active
low or falling edge-triggered interrupt signal to tell the processor
to read the data from the AD7890. Provided the read operation
is completed 500 ns before the rising edge of CONVST, the
AD7890 will operate to specification.
This scheme limits the throughput rate to 11.8 µs minimum. How-
ever, depending upon the response time of the microprocessor
to the interrupt signal and the time taken by the processor to
read the data, this may the fastest which the system could have
operated. In any case, the CONVST signal does not have to
have a 50:50 duty cycle. This can be tailored to optimize the
throughput rate of the part for a given system.
Alternatively, the CONVST signal can be used as a normal nar-
row pulsewidth. The rising edge of CONVST can be used as
an active high or rising edge-triggered interrupt. A software
delay of 5.9 µs can then be implemented before data is read
from the part.
CONVST
SCLK
RFS
TFS
TRACK/HOLD GOES
CONVERSION IS
INITIATED AND
INTO HOLD
CONVST
t
CONVERT
CONVERSION
ENDS 5.9 s
LATER
SERVICE OR
POLLING
ROUTINE
P INT
C
The C
how long after a new channel address is written to the part that a
conversion can take place. The reason behind this is two-fold.
Firstly, when the input channel to the AD7890 is changed, the
input voltage on this new channel is likely to be very different
from the previous channel voltage. Therefore, the part’s track/
hold has to acquire the new voltage before an accurate con-
version can take place. An internal pulse delays any conversion
start command (as well as the signal to send the track/hold
into hold) until after this pulse has timed out. The second
reason is to allow the user to connect external antialiasing or
signal conditioning circuitry between MUX OUT and SHA IN.
This external circuitry will introduce extra settling time into
the system. The C
extend the internal pulse to take this extra settling time into
account. Basically, varying the value of the capacitor on the
C
shows the relationship between the value of the C
tor and the internal delay.
EXT
EXT
FUNCTIONING
pin varies the duration of the internal pulse. Figure 7
EXT
64
56
48
40
32
24
16
8
0
input on the AD7890 provides a means of determining
0
SERIAL READ
OPERATIONS
AND WRITE
250
EXT
500
pin provides a means for the user to
C
OPERATIONS SHOULD
TO NEXT RISING EDGE
EXT
750
READ AND WRITE
END 500ns PRIOR
CAPACITANCE – pF
OF CONVST
1000
T
500ns MIN
A
1250
= +85 C
T
A
NEXT CONVST
T
= –40 C
1500
RISING EDGE
A
= +25 C
1750
EXT
2000
capaci-