AD9640BCPZ-150 Analog Devices Inc, AD9640BCPZ-150 Datasheet - Page 43

• Manufacturer Part Number: AD9640BCPZ-150
• Description: IC ADC 14BIT 150MSP 1.8V 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9640BCPZ-150

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 938mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXTERNAL MEMORY MAP
Table 25. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
0x0D
Register
Name
SPI Port
Configuration
(Global)
Chip ID
(Global)
Chip Grade
(Global)
Channel Index
Device Update
Power Modes
Global Clock
(Global)
Clock Divide
(Global)
Test Mode
(Local)
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
External
power-
down pin
function
(global)
0 = pdwn
1 = stndby
Open
Open
Reset PN
long gen
Speed grade ID
00 = 150 MSPS
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Bit 4
1
Open
Open
Open
Open
Open
Reset
PNshort
gen
Rev. B | Page 43 of 52
8-bit Chip ID[7:0]
(AD9640 = 0x11)
(default)
Bit 3
1
Open
Open
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checker board
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
Bit 1
LSB first
Open
Data
Channel B
(default)
Open
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
Open
0
Bit 0
(LSB)
Open
Data
Channel A
(default)
Transfer
Duty cycle
stabilizer
(default)
Default
Value
(Hex)
0x18
0x11
Read
only
Read
only
0x03
0x00
0x00
0x01
0x00
0x00
AD9640
Default
Notes/
Comments
The nibbles
are mirrored
so that
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
Speed grade
ID used to
differentiate
devices
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers
Synchronously
transfers data
from the
master shift
register to the
slave
Determines
various generic
modes of chip
operation
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active
When set,
the test data
is placed on
the output
pins in place of
normal data