AD9640BCPZ-150 Analog Devices Inc, AD9640BCPZ-150 Datasheet - Page 30

• Manufacturer Part Number: AD9640BCPZ-150
• Description: IC ADC 14BIT 150MSP 1.8V 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9640BCPZ-150

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 938mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9640
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 63, the power dissipated by the AD9640
is proportional to its sample rate. In CMOS output mode,
the digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (I
where N is the number of output bits (30 in the case of the AD9640
with the FD bits disabled). This maximum current occurs when
every output bit switches on every clock cycle, that is, a full-
scale square wave at the Nyquist frequency of f
the DRVDD current is established by the average number of
output bits switching, which is determined by the sample rate
and the characteristics of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken with the same operating conditions as the Typical
Performance Characteristics, with a 5 pF load on each output
driver.
1.25
0.75
0.25
1.25
0.75
0.25
I
1.0
0.5
1.0
0.5
DRVDD
Figure 63. AD9640-150 Power and Current vs. Clock Frequency
Figure 64. AD9640-125 Power and Current vs. Clock Frequency
0
0
0
0
= V
I
I
DVDD
DVDD
DRVDD
25
25
× C
ENCODE FREQUENCY (MHz)
ENCODE FREQUENCY (MHz)
50
LOAD
50
× f
TOTAL POWER
TOTAL POWER
I
CLK
AVDD
75
I
× N
AVDD
DRVDD
75
100
) can be calculated as
I
I
DRVDD
DRVDD
100
CLK
125
/2. In practice,
150
125
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
Rev. B | Page 30 of 52
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9640 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9640 to its normal operational mode. Note that PDWN is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
0.75
0.25
0.75
0.25
0.5
0.5
Figure 65. AD9640-105 Power and Current vs. Clock Frequency
0
Figure 66. AD9640-80 Power and Current vs. Clock Frequency
1
0
0
0
I
DVDD
I
DVDD
25
20
ENCODE FREQUENCY (MHz)
ENCODE FREQUENCY (MHz)
50
TOTAL POWER
40
TOTAL POWER
I
DRVDD
I
AVDD
75
60
I
AVDD
I
DRVDD
100
8
0
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0