AD7664AST Analog Devices Inc, AD7664AST Datasheet - Page 3

• Manufacturer Part Number: AD7664AST
• Description: IC ADC 16BIT UNIPOLAR 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7664AST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 115mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: EVAL-AD7664CBZ - BOARD EVALUATION FOR AD7664

TIMING SPECIFICATIONS
Parameter
REFER TO FIGURES 11 AND 12
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
NOTES
1
2
3
Specifications subject to change without notice.
REV. E
Parameter
TEMPERATURE RANGE
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
In Normal Mode.
Tested in Parallel Reading Mode.
In Impulse Mode.
With all digital inputs forced to OVDD or OGND, respect
Contact factory for extended temperature range.
Convert Pulse Width
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH (INVSCLK Low)
Internal SCLK LOW (INVSCLK Low)
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
Specified Performance
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
8
3
2
3
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Conditions
T
MIN
ively.
to T
MAX
2
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
–3–
Min
–40
Min
5
1.75/2/2.25
10
250
10
45
5
4
40
30
9.5
4.5
3
3
5
3
5
5
25
10
10
L
of 10 pF; otherwise, the load is 60 pF maximum.
Typ
Typ
2
25/275/525
1/1.25/1.5
50
Max
+85
Max
Note 1
25
1.5/1.75/2
1.5/1.75/2
1.5/1.75/2
40
15
10
10
10
75
10
10
10
2.75/3/3.25
16
AD7664
Unit
°C
Unit
ns
µs
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns