MAX1301BEUP+ Maxim Integrated Products, MAX1301BEUP+ Datasheet - Page 18

• Manufacturer Part Number: MAX1301BEUP+
• Description: IC ADC 16BIT SER 4CH LP 20TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1301BEUP+

• Number Of Bits: 16
• Sampling Rate (per Second): 115k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 105.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1300/MAX1301 differential common-mode
range (V
valid conversion results. The differential common-mode
range is defined as:
In addition to the common-mode input voltage limitations,
each individual analog input must be limited to ±16.5V
with respect to AGND1.
8- and 4-Channel, ±3 x V
Serial 16-Bit ADCs
Table 3. Input Data Word Formats
Table 4. Channel Selection in Single-Ended Mode (DIF/S S G G L L = 0)
Table 5. Channel Selection in True-Differential Mode (DIF/S S G G L L = 1)
18
Conversion-Start Byte
(Tables 4 and 5)
Analog-Input Configuration Byte
(Table 2)
Mode-Control Byte
(Table 7)
C2
C2
CHANNEL-SELECT BIT
CHANNEL-SELECT BIT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
______________________________________________________________________________________
CMDR
OPERATION
Differential Common-Mode Range
V
C1
C1
CMDR
) must remain within -14V to +10V to obtain
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
=
C0
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(
CH
_
+
)
CH0
CH0
2
+
+
+
(
(START)
CH
D7
1
1
1
_
−
)
CH1
CH1
+
-
D6
C2
C2
M2
CH2
CH2
+
+
M1
D5
C1
C1
REF
The range-select bits R[2:0] in the analog input config-
uration bytes determine the full-scale range for the cor-
responding channel (Tables 2 and 6). Figures 9, 10,
and 11 show the valid analog input voltage ranges for
the MAX1300/MAX1301 when operating with FSR =
(±3 x V
respectively. The shaded area contains the valid com-
mon-mode voltage ranges that support the entire FSR.
CH3
CH3
+
-
REF)
RESERVED
RESERVED
RESERVED
RESERVED
CHANNEL
CHANNEL
D4
C0
C0
M0
Multirange Inputs,
DATA BIT
CH4
CH4
/2, FSR = ±3 x V
+
+
DIF/SGL
D3
0
1
CH5
CH5
+
-
REF
D2
R2
0
0
CH6
CH6
+
+
, and FSR = ±6 x V
D1
R1
CH7
CH7
0
0
+
-
AGND1
AGND1
D0
R0
0
0
-
-
-
-
-
-
-
-
REF
,