AD9271BSVZ-25 Analog Devices Inc, AD9271BSVZ-25 Datasheet - Page 8

IC ADC OCT 12BIT 25MSPS 100-TQFP

AD9271BSVZ-25

Manufacturer Part Number
AD9271BSVZ-25
Description
IC ADC OCT 12BIT 25MSPS 100-TQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9271BSVZ-25

Data Interface
Serial, SPI™
Number Of Bits
12
Sampling Rate (per Second)
25M
Number Of Converters
8
Power Dissipation (max)
1.06W
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad
Resolution (bits)
12bit
Sampling Rate
50MSPS
Input Channel Type
Differential, Single Ended
Supply Voltage Range - Digital
1.7V To 1.9V
Supply Current
505mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9271BSVZ-25
Manufacturer:
AD
Quantity:
1 600
Part Number:
AD9271BSVZ-25
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9271
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Can be adjusted via the SPI interface.
Measurements were made using a part soldered to FR-4 material.
t
SAMPLE
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data-to-Data Skew (t
Wake-Up Time (Standby), V
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Uncertainty (Jitter)
/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.
2
1
F
R
) (20% to 80%)
) (20% to 80%)
2, 3
FRAME
PD
DATA
DATA-MAX
)
)
)
EL
4
4
EH
FCO
CPD
)
)
GAIN
)
− t
)
4
DATA-MIN
= 0.5 V
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
Min
50
1.5
1.5
(t
(t
SAMPLE
SAMPLE
Rev. B | Page 8 of 60
/24) − 300
/24) − 300
Typ
10.0
10.0
2.3
300
300
2.3
t
(t
(t
(t
±50
1
1
8
<1
FCO
SAMPLE
SAMPLE
SAMPLE
+
/24)
/24)
/24)
Max
(t
(t
10
3.1
3.1
±200
SAMPLE
SAMPLE
/24) + 300
/24) + 300
Unit
μs
ms
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
Clock
cycles
ps rms

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