AD9255BCPZ-80 Analog Devices Inc, AD9255BCPZ-80 Datasheet - Page 37

• Manufacturer Part Number: AD9255BCPZ-80
• Description: IC ADC 14BIT 80MSPS 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9255BCPZ-80

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Number Of Converters: 1
• Power Dissipation (max): 248mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 80MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr.
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Transfer Register
0xFF
ADC Functions Registers
0x08
0x09
0x0D
0x0E
Register
Name
SPI port
configuration
Chip ID
Chip grade
Transfer
Power
modes
Global clock
Test mode
BIST enable
Bit 7 (MSB)
0
Open
Open
1
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
External power-
down pin
function
0 = power-
down
1 = standby
Open
Reset PN23
generator
Open
8-Bit Chip ID[7:0], AD9255 = 0x65 (default)
Speed grade ID
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Rev. A | Page 37 of 44
Bit 4
1
Open
Open
Open
Reset PN9
generator
Open
Bit 3
1
Open
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Reset BIST
sequence
100 = alternating checkerboard
111 = one/zero word toggle
101 = PN 23 sequence
001 = midscale short
110 = PN 9 sequence
Output test mode
000 = off (default)
011 = negative FS
010 = positive FS
Bit 1
LSB
first
Open
Open
Open
Open
01 = full power-
10 = standby
power-down
00 = normal
11 = normal
operation
operation
Internal
mode
down
Bit 0 (LSB)
0
Open
Transfer
Duty
cycle
stabilizer
(default)
BIST
enable
Default
Value
(Hex)
0x18
0x65
0x00
0x80
0x01
0x00
0x04
Default Notes/
Comments
The nibbles are
mirrored so
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
Speed grade ID
used to
differentiate
devices; read
only
Synchronously
transfers data
from the
master shift
register to the
slave
Determines
various generic
modes of chip
operation
When this
register is set,
the test data is
placed on the
output pins in
place of normal
data
AD9255