AD9255BCPZ-80 Analog Devices Inc, AD9255BCPZ-80 Datasheet - Page 32

• Manufacturer Part Number: AD9255BCPZ-80
• Description: IC ADC 14BIT 80MSPS 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9255BCPZ-80

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Number Of Converters: 1
• Power Dissipation (max): 248mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 80MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9255
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. In addition, when using the SPI
mode, the user can change the function of the external PDWN pin
to either place the part in power-down or standby mode. See the
Memory Map Register Descriptions section for more details.
DIGITAL OUTPUTS
The AD9255 output drivers can be configured to interface with
1.8 V CMOS logic families. The AD9255 can also be configured
for LVDS outputs using a DRVDD supply voltage of 1.8 V. The
AD9255 defaults to CMOS output mode but can be placed into
LVDS mode either by setting the LVDS pin high or by using the
SPI port to place the part into LVDS mode. Because most users do
not toggle between CMOS and LVDS mode during operation, use
of the LVDS pin is recommended to avoid any power-up loading
issues on the CMOS configured outputs.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies, which may affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
In LVDS output mode, two output drive levels can be selected,
either ANSI LVDS or reduced swing LVDS mode. Using the
reduced swing LVDS mode lowers the DRVDD current and
reduces power consumption. The reduced swing LVDS mode
can be selected by asserting the LVDS_RS pin or by selecting
this mode via the SPI port.
The output data format is selected for either offset binary or
twos complement by setting the SCLK/DFS pin when operating in
the external pin mode (see Table 12).
As detailed in AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 13. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. A | Page 32 of 44
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage
at Pin
AGND
SVDD
Digital Output Enable Function (OEB)
The AD9255 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI interface. If the OEB pin is low, the output data
drivers and DCOs are enabled. If the OEB pin is high, the output
data drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data and DCO outputs can be
three-stated by using the output enable bar bit in Register 0x14.
TIMING
The AD9255 provides latched data with a pipeline delay of
12 clock cycles (12.5 clock cycles in LVDS mode). Data outputs
are available one propagation delay (t
the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9255. These tran-
sients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9255 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9255 provides a single data clock output (DCO) pin in
CMOS output mode and two differential data clock output (DCO)
pins in LVDS mode intended for capturing the data in an external
register. In CMOS output mode, the data outputs are valid on the
rising edge of DCO, unless the DCO clock polarity has been
changed via the SPI. In LVDS output mode, data is output as
double data rate with the even numbered output bits transitioning
near the rising edge of DCO and the odd numbered output bits
transitioning near the falling edge of DCO. See Figure 2 for a
graphical timing description.
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
SCLK/DFS
Offset binary (default)
Twos complement
PD
) after the rising edge of
SDIO/DCS
DCS disabled
DCS enabled (default)
OR
1
0
0
0
1