AD7731BNZ Analog Devices Inc, AD7731BNZ Datasheet - Page 7

• Manufacturer Part Number: AD7731BNZ
• Description: IC ADC 24BIT SIGMA-DELTA 24DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7731BNZ

• Data Interface: DSP, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 6.4k
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 6.4kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7731EBZ - BOARD EVALUATION FOR AD7731
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. A
Pin
No.
1
2
REV. 0
CAPACITOR CHARGING CURRENTS
TO THE SAMPLING CAPACITOR OF
ON-CHIP BEFORE BEING APPLIED
THE INPUT SIGNAL IS BUFFERED
THE SIGMA DELTA MODULATOR.
THE INPUT IS CHOPPEDAND THE OUTPUT OF
FROM THE ANALOG INPUT PINS
THIS ISOLATES THE SAMPLING
ANALOG
CAN BE CHOPPED. IN CHOPPING MODE,
THE FIRST STAGE FILTER IS CHOPPED
INPUT
Pin
Mnemonic
SCLK
MCLK IN
REMOVING ERRORS IN THAT PATH.
THE ANALOG INPUT TO THE PART
THE DEFAULT CONDITION IS
SEE PAGE 23
BUFFER
INPUT CHOPPING
CHOPPING DISABLED
SEE PAGE 25
CHOP
Function
Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer
serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a
continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-
mitted to or from the AD7731 in smaller batches of data.
Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock.
A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN
pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified
with a clock input frequency of 4.9152 MHz.
BUFFER
FREQUENCY 1-BIT DATA STREAM
MODULATOR PROVIDES A HIGH-
SIGMA DELTA MODULATOR.THE
INCORPORATED AROUND THE
PGA & SIGMA-DELTA
CAPABILITY OF THE PART IS
THE PROGRAMMABLE GAIN
TO THE DIGITAL FILTER.
MODULATOR
SEE PAGE 24
SINC
THE ONLY FILTERING PERFORMED
THE FIRST STAGE OF THE DIGITAL
FILTER CAN BE PROGRAMMED. IN
SKIP MODE, THE SINC
FILTERING ON THE PART IS THE
RATE AND BANDWIDTH OF THIS
3
SIGMA-DELTA
FILTER. THE OUTPUT UPDATE
MODULATOR
SINC
PGA &
SEE PAGE 25
ON THE P3T.
3
Figure 3. Signal Processing Chain
PIN FUNCTION DESCRIPTIONS
FILTER
MCLK OUT
MCLK IN
AIN3/D1
RESET
3
AGND
SYNC
SCLK
AV
PIN CONFIGURATION
FILTER IS
AIN1
AIN2
POL
NC
DD
THE OUTPUT OF THE FIRST STAGE
OF FILTERING ON THE PART CAN
BE CHOPPED. THE DEFAULT
OUTPUT CHOPPING
CONDITION IS CHOPPING
10
11
12
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
FILTER
SINC
(Not to Scale)
SEE PAGE 25
DISABLED
AD7731
TOP VIEW
3
–7–
THE ONLY FILTERING PERFORMED
SECOND STAGE OF FILTERING ON
THE PART. THE SINC
IN SKIP MODE, THERE IS NO
ON THE PART. THIS IS THE
SECOND STAGE FILTER
19
18
17
16
15
14
13
CHOP
24
23
22
21
20
SKIP MODE
SEE PAGE 25
DGND
DV
DIN
DOUT
AIN6
AIN5
REF IN(–)
REF IN(+)
AIN4/D0
RDY
CS
STANDBY
DD
3
ENABLED AND A STEP CHANGE ON
THE SECOND STAGE FILTERING IS
FILTER UNTIL THE FIR FILTER HAS
FILTER IS
THE INPUT HAS BEEN DETECTED,
PERFORMED BY THE FASTSTEP™
WHEN FASTSTEP™ MODE IS
FASTSTEP™ FILTER
FASTSTEP™
FIR FILTER
FULLY SETTLED.
FILTER
22-TAP
SEE PAGE 28
SKIP
YY
OF THE DIGITAL FILTERING ON THE PART IS
OPERATING MODE OF THE SECOND STAGE
A FIXED 22-TAP FIR FILTER. IN SKIP MODE,
STAGE FILTERING IS PERFORMED BY THE
FAST STEP FILTER UNTIL THE OUTPUT OF
STEP INPUT IS DETECTED, THE SECOND
FASTSTEP™ MODE IS ENABLED AND A
THIS FIR FILTER IS BYPASSED. WHEN
WITH SKIP DISABLED, THE NORMAL
THIS FILTER HAS FULLY SETTLED
22-TAP FIR FILTER
SCALING
OUTPUT
DIGITAL FILTER IS SCALED BY THE
BEFORE BEING PROVIDED AS THE
THE OUTPUT WORD FROM THE
CALIBRATION COEFFICIENTS
SEE PAGE 26
OUTPUT SCALING
CONVERSION RESULT
SEE PAGE 29
AD7731
DIGITAL
OUTPUT