LTC2435-1IGN#TRPBF Linear Technology, LTC2435-1IGN#TRPBF Datasheet - Page 20

• Manufacturer Part Number: LTC2435-1IGN#TRPBF
• Description: IC ADC DIFF I/REF 20BIT 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2435-1IGN#TRPBF

• Number Of Bits: 20
• Sampling Rate (per Second): 13.75
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2435/LTC2435-1
APPLICATIO S I FOR ATIO
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion is over. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
20
(EXTERNAL)
SDO
SCK
DATA OUTPUT
CS
SLEEP
U
BIT 0
EOC
CONVERSION
Hi-Z
U
TEST EOC
CC
SLEEP
TEST EOC
exceeds 2.2V. The level
Figure 9. External Serial Clock, Reduced Data Output Length
Hi-Z
W
ANALOG INPUT RANGE
–0.5V
Hi-Z
REF
1, 7, 8, 9, 10, 15, 16
0.1V TO V
REFERENCE
SLEEP
BIT 23
TO 0.5V
EOC
U
VOLTAGE
1μF
2.7V TO 5.5V
REF
CC
BIT 22
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
LTC2435-1
+
–
LTC2435/
+
–
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 11.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the conversion is over.
BIT 21
SDO
SIG
SCK
CS
F
O
14
13
12
11
DATA OUTPUT
BIT 20
MSB
3-WIRE
SPI INTERFACE
V
CC
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
BIT 19
BIT 9
BIT 8
CONVERSION
Hi-Z
TEST EOC
2435 F09
24351fb