MAX1401EAI+ Maxim Integrated Products, MAX1401EAI+ Datasheet - Page 11

• Manufacturer Part Number: MAX1401EAI+
• Description: IC ADC 18BIT LP 28-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1401EAI+

• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 750µW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Number Of Adc Inputs: 5
• Architecture: Delta-Sigma
• Conversion Rate: 4.8 KSPs
• Resolution: 18 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: External
• Supply Voltage (max): 3 V
• Maximum Power Dissipation: 21.45 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Signal Type: Pseudo-Differential, Differential
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
MUXOUT+
MUXOUT-
CLKOUT
ADCIN+
ADCIN-
RESET
NAME
CLKIN
AGND
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
CS
V+
______________________________________________________________________________________
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT uncon-
nected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1.
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.
Chip-Select Input. This active-low logic input is used to enable the digital interface. With CS hard-wired
low, the MAX1401 operates in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to
the device. CS is used either to select the device in systems with more than one device on the serial bus,
or as a frame-synchronization signal for the MAX1401 when a continuous SCLK is used.
Active-Low Reset Input. Drive low to reset the control logic, interface logic, digital filter, and analog modu-
lator to power-on status. RESET must be high and CLKIN must be toggling in order to exit reset.
Positive Analog Mux Output. The positive differential output signal from the part’s internal input multiplex-
er. Use this signal in conjunction with MUXOUT- and a high-quality external amplifier for additional signal
processing before conversion. Return the processed output through ADCIN+ and ADCIN-. Connect
MUXOUT+ directly to ADCIN+ if external processing is not required.
Negative Analog Mux Output. The negative differential output signal from the part’s internal input multi-
plexer. Use this signal in conjunction with MUXOUT+ and a high-quality external amplifier for additional
signal processing before conversion. Return the processed output through ADCIN+ and ADCIN-.
Connect MUXOUT- directly to ADCIN- if external processing is not required.
Positive Analog Input. A direct input to the positive buffer and the positive differential input terminal of the
ADC, bypassing the input mux. This signal forms a differential input pair with ADCIN-. Connect ADCIN+ to
MUXOUT+ when direct access is not required.
Negative Analog Input. A direct input to the negative buffer and the negative differential input terminal of
the ADC - bypassing the input mux. This signal forms a differential input pair with ADCIN+. Connect
ADCIN- to MUXOUT- when direct access is not required.
Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.
Analog Positive Supply Voltage (+2.7V to +3.6V)
Analog Input Channel 1. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN1/AIN2 differential analog input pair (see On-Chip Registers section).
Analog Input Channel 2. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN1/AIN2 differential analog input pair (see On-Chip Registers section).
Analog Input Channel 3. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN3/AIN4 differential analog input pair (see On-Chip Registers section).
Analog Input Channel 4. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN3/AIN4 differential analog input pair (see On-Chip Registers section).
Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6 (see On-Chip
Registers section).
Analog Input 6. May be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see On-Chip Registers section).
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
FUNCTION
Pin Description
11