MAX1192ETI+ Maxim Integrated Products, MAX1192ETI+ Datasheet - Page 15

• Manufacturer Part Number: MAX1192ETI+
• Description: IC ADC 8BIT 22MSPS DUAL 28-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1192ETI+

• Number Of Bits: 8
• Sampling Rate (per Second): 22M
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN Exposed Pad
• Number Of Adc Inputs: 2
• Conversion Rate: 22 MSPs
• Resolution: 8 bit
• Input Type: Differential
• Interface Type: Parallel
• Voltage Reference: Internal 2.048 V or External
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 1667 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1. Pipeline Architecture—Stage Blocks
Figure 2. MAX1192 Functional Diagram
INA+
INA-
PIN
23
24
25
26
27
—
FLASH
T/H
ADC
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
NAME
REFIN
REFN
COM
REFP
REFIN
PD0
REFP
REFN
COM
INA+
INB+
INA-
INB-
EP
______________________________________________________________________________________
T/H
STAGE 1
1.5 BITS
Power-Down Digital Input 0. See Table 3.
Reference Input. Internally pulled up to V
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
Negative Reference I/O. Conversion range is ±(V
capacitor.
Positive Reference I/O. Conversion range is ±(V
capacitor.
Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND.
DAC
DIGITAL ERROR CORRECTION
T/H
T/H
STAGE 2
+
∑
D0–D7
-
SYSTEM AND
REFERENCE
PIPELINE
PIPELINE
CIRCUITS
ADC
ADC
BIAS
A
B
x2
STAGE 7
/
/
DEC
DEC
MULTIPLEXER
The MAX1192 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeated
until the signal has been processed by all stages. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes.
DD
.
FUNCTION
Figure
REFP
REFP
MAX1192
Pin Description (continued)
- V
- V
2 shows the MAX1192 functional diagram.
REFN
REFN
). Bypass REFP to GND with a 0.33µF
DRIVERS
OUTPUT
TIMING
). Bypass REFN to GND with a 0.33µF
CONTROL
POWER
Detailed Description
OV
V
GND
PD0
PD1
D0–D7
A/B
OGND
CLK
DD
DD
15