AD9233BCPZ-125 Analog Devices Inc, AD9233BCPZ-125 Datasheet - Page 25

• Manufacturer Part Number: AD9233BCPZ-125
• Description: IC ADC 12BIT 80/105/125 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9233BCPZ-125

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Number Of Converters: 3
• Power Dissipation (max): 425mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9233-125EBZ - BOARD EVALUATION FOR AD9233
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 15. Memory Map Register
Addr
(Hex)
Chip Configuration Registers
00
01
02
Device Index and Transfer Registers
FF
Global ADC Functions
08
09
Flexible ADC Functions
10
Parameter
Name
chip_port_config
chip_id
chip_grade
device_update
modes
clock
offset
Bit 7
(MSB)
0
Open
Open
Open
Open
Bit 6
LSB
First
0 = Off
(Default)
1 = On
Open
Open
Open
Open
Bit 5
Soft
Reset
0 = Off
(Default)
1 = On
Open
Open
PDWN
0—Full
1—
Standby
Open
Digital Offset Adjust <5:0>
011111
011110
011101
…
000010
000001
000000
111111
111110
111101
...
100001
100000
(AD9233 = 0x00), (Default)
Open
Open
Bit 4
1
Open
Open
8-Bit Chip ID Bits 7:0
Rev. A | Page 25 of 44
Bit 3
1
Child ID
0 =
125
MSPS,
1 =
105
MSPS
Open
Open
Open
Bit 2
Soft
Reset
0 = Off
(Default)
1 = On
Open
Open
Internal Power-Down Mode
000—Normal (Power-Up)
001—Full Power-Down
010—Standby
011—Normal (Power-Up)
Note: External PDWN pin
overrides this setting.
Open
Offset in LSBs
+7 3/4
+7 1/2
+7 1/4
+1/2
+1/4
0
−1/4
−1/2
−3/4
−7 3/4
−8
Bit 1
LSB
First
0 = Off
(Default)
1 = On
Open
Open
Open
Bit 0
(LSB)
0
Open
SW Transfer
Duty Cycle
Stabilizer
0—
Disabled
1—Enabled
Default
Value
(Hex)
0x18
Read-
Only
Read-
Only
0x00
0x00
0x01
0x00
Default
Notes/
Comments
The nibbles
should be
mirrored. See
Interfacing to
High Speed
ADCs via SPI
User
Default is
unique chip ID,
different for
each device.
Child ID used
to differentiate
speed grades.
Synchronously
transfers data
from the
master
shift register to
the slave.
Determines
various generic
modes of chip
operation. See
Power
Dissipation
and Standby
Mode and
SPI-Accessible
Features
sections.
See Clock Duty
Cycle and
SPI-Accessible
Features
sections.
Adjustable for
offset inherent
in the
converter.
See SPI-
Accessible
Features
section.
AD9233
Manual.