AD9233BCPZ-125 Analog Devices Inc, AD9233BCPZ-125 Datasheet - Page 21

• Manufacturer Part Number: AD9233BCPZ-125
• Description: IC ADC 12BIT 80/105/125 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9233BCPZ-125

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Number Of Converters: 3
• Power Dissipation (max): 425mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9233-125EBZ - BOARD EVALUATION FOR AD9233
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Power-Down Mode
By asserting the PDWN pin high, the AD9233 is placed in
power-down mode. In this state, the ADC typically dissipates
1.8 mW. During power-down, the output drivers are placed in a
high impedance state. Reasserting the PDWN pin low returns
the AD9233 to its normal operational mode. This pin is both
1.8 V and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling
capacitor on REFT and REFB, it takes approximately 0.25 ms
to fully discharge the reference buffer decoupling capacitor and
0.35 ms to restore full operation.
Standby Mode
When using the SPI port interface, the user can place the ADC
in power-down or standby modes. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map
section for more details.
DIGITAL OUTPUTS
The AD9233 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that can affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts can require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when
operating in the external pin mode (see Table 10). As detailed in
the
data format can be selected for either offset binary, twos
complement, or Gray code when using the SPI control.
Table 12. Output Data Format
Condition (V)
VIN+ − VIN− < –VREF – 0.5 LSB
VIN+ − VIN− = –VREF
VIN+ − VIN− = 0
VIN+ − VIN− = +VREF – 1.0 LSB
VIN+ − VIN− > +VREF – 0.5 LSB
Interfacing to High Speed ADCs via SPI User
Binary Output Mode
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Manual, the
Rev. A | Page 21 of 44
Twos Complement Mode
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
Out-of-Range (OR) Condition
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same pipeline
latency as the digital data.
OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 55. OR remains high until the
analog input returns to within the input range and another
conversion is completed. By logically AND’ing the OR bit with
the MSB and its complement, overrange high or underrange
low conditions can be detected. Table 11 is a truth table for the
overrange/underrange circuit in Figure 56, which uses NAND
gates.
Table 11. Overrange/Underrange Truth Table
OR
0
0
1
1
Digital Output Enable Function (OEB)
The AD9233 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the output
data drivers are placed in a high impedance state. This is not
intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
MSB
MSB
OR DATA OUTPUTS
OR
1
0
0
0
0
1
Figure 55. OR Relation to Input Voltage and Output Data
MSB
0
1
0
1
1111
1111
1111
0000
0000
0000
1111
1111
1111
0000
0000
0000
Figure 56. Overrange/Underrange Logic
Analog Input Is:
Within Range
Within Range
Underrange
Overrange
1111
1111
1110
0001
0000
0000
Gray Code Mode (SPI Accessible)
1100 0000 0000
1100 0000 0000
0000 0000 0000
1000 0000 0000
1000 0000 0000
–FS – 1/2 LSB
OR
–FS
–FS + 1/2 LSB
+FS – 1/2 LSB
+FS – 1 LSB
OVER = 1
UNDER = 1
+FS
AD9233
OR
1
0
0
0
1