MAX146ACAP+ Maxim Integrated Products, MAX146ACAP+ Datasheet - Page 10

• Manufacturer Part Number: MAX146ACAP+
• Description: IC ADC LP 12-BIT 133KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX146ACAP+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
where R
input signal, and t
that source impedances below 1kΩ do not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Figure 5. Quick-Look Circuit
10
ACQ
MAX872
OPTIONAL FOR MAX146,
REQUIRED FOR MAX147
______________________________________________________________________________________
, is the maximum time the device takes to acquire
+3V
COMP
V
OUT
IN
ANALOG
2.500V
= 9kΩ, R
INPUT
0V TO
t
ACQ
1000pF
0.01µF
= 9 x (R
ACQ
S
= the source impedance of the
C1
0.1µF
is never less than 1.5µs. Note
2.5V
+3V
S
+ R
CH7
VREF
REFADJ
IN
MAX146
MAX147
Input Bandwidth
) x 16pF
SSTRB
DGND
AGND
DOUT
SHDN
SCLK
COM
V
DIN
CS
DD
N.C.
+3V
Internal protection diodes, which clamp the analog input
to V
from AGND - 0.3V to V
However, for accurate conversions near full scale, the
inputs must not exceed V
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
To quickly evaluate the MAX146/MAX147’s analog per-
formance, use the circuit of Figure 5. The MAX146/
MAX147 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in con-
trol bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 15 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
occur on the falling edge of SCLK.
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
DD
0.1µF
and AGND, allow the channel input pins to swing
+3V
OSCILLATOR
2MHz
CH1
Analog Input Protection
DD
DD
OSCILLOSCOPE
CH2
+ 0.3V without damage.
by more than 50mV or be
CH3
Quick Look
CH4
SCLK
SSTRB
DOUT*