MAX1248BEEE+ Maxim Integrated Products, MAX1248BEEE+ Datasheet - Page 5

• Manufacturer Part Number: MAX1248BEEE+
• Description: IC ADC 10BIT SERIAL 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1248BEEE+

• Number Of Bits: 10
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.6mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 842 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
Note 3: MAX1248—internal reference, offset nulled; MAX1249 — external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
Note 7 Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10 Guaranteed by design. Not subject to production testing.
Note 11: The MAX1249 typically draws 400 A less than the values shown.
Note 12: Measured as V
TIMING CHARACTERISTICS
(V
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
DD
= +2.7V to +5.25V, T
been calibrated.
PARAMETER
DD
_______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 4-Channel,
= 2.7V; COM = 0V; unipolar single-ended input mode.
FS
A
= T
(2.7V) - V
MIN
to T
SYMBOL
FS
t
SSTRB
MAX
t
t
t
t
t
t
(5.25V) .
ACQ
t
t
CSH
t
t
t
CSS
t
SDV
SCK
t
STR
DH
DO
CH
DS
DV
CL
TR
, unless otherwise noted.)
Figure 1
Figure 1
Figure 2
Figure 1
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 10)
Serial 10-Bit ADCs in QSOP-16
MAX124_ _C/E
MAX124_ _M
CONDITIONS
DD
.
MIN
100
100
200
200
1.5
20
20
0
0
TYP
MAX
200
240
240
240
240
240
240
0
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5