KAD5512HP-25Q48 Intersil, KAD5512HP-25Q48 Datasheet - Page 10

IC ADC 12BIT 250MSPS SGL 48-QFN

KAD5512HP-25Q48

Manufacturer Part Number
KAD5512HP-25Q48
Description
IC ADC 12BIT 250MSPS SGL 48-QFN
Manufacturer
Intersil
Series
FemtoCharge™r
Datasheet

Specifications of KAD5512HP-25Q48

Number Of Bits
12
Sampling Rate (per Second)
250M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
463mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VQFN
For Use With
KDC5512-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512H-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512HEVAL - DAUGHTER CARD FOR KAD5512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KAD5512HP-25Q48
Manufacturer:
UMS
Quantity:
1 400
Pin Descriptions - 72QFN
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection), SDR is the default state at
power-up for the 72pin package
Exposed Paddle
PIN NUMBER
46
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64
66
67
68
69
70
LVDS [LVCMOS] NAME
10
(Continued)
CLKOUTN
CLKOUTP
[CLKOUT]
OUTFMT
RLVDS
D10N
SCLK
AVSS
D10P
[D10]
D11N
D11P
SDIO
[D11]
ORN
ORP
SDO
[NC]
D6N
[NC]
D6P
D7N
[NC]
D7P
D8N
[NC]
D8P
D9N
[NC]
D9P
[NC]
[NC]
[NC]
[OR]
CSB
[D6]
[D7]
[D8]
[D9]
LVDS Bias Resistor (connect to OVSS with a 10kΩ,
1% resistor)
LVDS Clock Output Complement
[NC in LVCMOS]
LVDS Clock Output True
[LVCMOS CLKOUT]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
LVDS Bit 6 Output True
[LVCMOS Bit 6]
LVDS Bit 7 Output Complement
[NC in LVCMOS]
LVDS Bit 7 Output True
[LVCMOS Bit 7]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
LVDS Bit 8 Output True
[LVCMOS Bit 8]
LVDS Bit 9 Output Complement
[NC in LVCMOS]
LVDS Bit 9 Output True
[LVCMOS Bit 9]
LVDS Bit 10 Output Complement
[NC in LVCMOS]
LVDS Bit 10 Output True
[LVCMOS Bit 10]
LVDS Bit 11 Output Complement
[NC in LVCMOS]
LVDS Bit 11 Output True
[LVCMOS Bit 11]
LVDS Over Range Complement
[NC in LVCMOS]
LVDS Over Range True
[LVCMOS Over Range]
SPI Serial Data Output (4.7kΩ pull-up to OVDD is
required)
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Output Data Format (Two’s Comp., Gray Code, Offset
Binary)
Analog Ground
KAD5512HP
LVDS [LVCMOS] FUNCTION
SDR MODE
DDR Logical Bits 7,6 (LVDS)
DDR Logical Bits 7,6 (LVDS
or CMOS)
NC in DDR
NC in DDR
DDR Logical Bits 9, 8 (LVDS)
DDR Logical Bits 9, 8 (LVDS
or CMOS)
NC in DDR
NC in DDR
DDR Logical Bits 11, 10
(LVDS)
DDR Logical Bits 11, 10
(LVDS or CMOS)
NC in DDR
NC in DDR
DDR MODE COMMENTS
October 1, 2009
FN6808.3

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