KAD5512HP-17Q72 Intersil, KAD5512HP-17Q72 Datasheet
KAD5512HP-17Q72
Specifications of KAD5512HP-17Q72
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KAD5512HP-17Q72 Summary of contents
Page 1
... KAD5512 family of 12-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates 250MSPS. The KAD5512HP is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset ...
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... Ordering Information PART NUMBER KAD5512HP-25Q72 (Note 1) KAD5512HP-21Q72 (Note 1) KAD5512HP-17Q72 (Note 1) KAD5512HP-12Q72 (Note 1) KAD5512HP-25Q48 (Note 2) KAD5512HP-21Q48 (Note 2) KAD5512HP-17Q48 (Note 2) KAD5512HP-12Q48 (Note 2) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Analog Input ............................................................... 18 Clock Input ................................................................. 19 Jitter............................................................................ 20 Voltage Reference...................................................... 20 Digital Outputs ............................................................ 20 Over-Range Indicator ................................................. 20 Power Dissipation....................................................... 20 Nap/Sleep................................................................... 21 Data Format ............................................................... 21 3 KAD5512HP Serial Peripheral Interface ........................................... 22 SPI Physical Interface................................................ 23 SPI Configuration....................................................... 24 Device Information ..................................................... 24 Indexed Device Configuration/Control ....................... 24 Global Device Configuration/Control.......................... 25 Device Test ................................................................ 27 SPI Memory Map ....................................................... 28 Equivalent Circuits ....................................................... 29 72 Pin/48 Pin Package Options ...
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... Maximum Conversion Rate SAMPLE KAD5512HP-17 KAD5512HP-12 (Note 4) (Note 4) TYP MAX MIN TYP MAX UNITS 1.47 1.54 1.40 1.47 1.54 500 500 2.6 2 ppm/°C ±2 10 -10 ±2 10 ± ...
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... Maximum Conversion Rate SAMPLE KAD5512HP-17 KAD5512HP-12 (Note 4) (Note 4) TYP MAX MIN TYP MAX UNITS 43 42 -36 -36 378 406 345 376 339 309 136 151 ...
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... CONDITIONS MIN -1dBFS Maximum Conversion Rate IN SAMPLE KAD5512HP-17 KAD5512HP-12 (Note 4) (Note 4) MAX MIN TYP MAX MIN TYP 87.3 84.9 70 82.0 70 81.7 79.2 80.3 75.1 75.5 61.3 61.6 48.7 50.2 -94.6 -94.8 -91.7 -85.7 -12 -12 - 950 950 specifications apply for 10pF load on each digital ...
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... LATENCY = L CYCLES CLKOUT ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS D[10/8/6/4/2/0] N-L N FIGURE 2A. DDR FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 20 7 KAD5512HP CONDITIONS MIN V 3mA Mode T V 3mA Mode 950 -500µA OVDD - 0 ...
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... The SPI may operate asynchronously with respect to the ADC sample clock 12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). 8 KAD5512HP CONDITION SYMBOL t A ...
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... D4P [D4] 43 D5N [NC] 44 D5P [D5] 9 KAD5512HP LVDS [LVCMOS] FUNCTION SDR MODE 1.8V Analog Supply Do Not Connect Analog Ground Analog Input Negative, Positive Common Mode Output Clock Divider Control Clock Input True, Complement Output Mode (LVDS, LVCMOS) Power Control (Nap, Sleep modes) Power On Reset (Active Low, see “ ...
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... OUTFMT Exposed Paddle AVSS NOTE: LVCMOS Output Mode Functionality is shown in brackets ( Connection), SDR is the default state at power-up for the 72pin package 10 KAD5512HP LVDS [LVCMOS] FUNCTION SDR MODE LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor) LVDS Clock Output Complement [NC in LVCMOS] ...
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... Pinout AVDD 1 DNC 2 DNC 3 4 DNC 5 DNC 6 AVDD 7 AVSS AVSS 8 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC KAD5512HP KAD5512HP (72 LD QFN) TOP VIEW Connect Thermal Pad to AVSS D8P 53 D8N 52 D7P 51 D7N 50 D6P 49 D6N 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS ...
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... KAD5512HP LVDS [LVCMOS] NAME AVDD 1.8V Analog Supply DNC Do Not Connect AVSS Analog Ground VINN, VINP Analog Input Negative, Positive VCM Common Mode Output CLKP, CLKN Clock Input True, Complement NAPSLP Power Control (Nap, Sleep modes) RESETN Power On Reset (Active Low, see “User-Initiated Reset” on page 18) ...
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... KAD5512HP LVDS [LVCMOS] NAME SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) CSB SPI Chip Select (active low) SCLK SPI Clock SDIO SPI Serial Data Input/Output AVSS Analog Ground KAD5512HP (48 LD QFN) TOP VIEW Connect Thermal Pad to AVSS 13 14 ...
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... SNR 100 130 160 SAMPLE RATE (MSPS) FIGURE 7. SNR AND SFDR KAD5512HP All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). 600M 800M 1G IN SNR (dBc) -100 -110 -120 ...
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... CODE FIGURE 13. NOISE HISTOGRAM 15 KAD5512HP All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). (Continued) 0.5 0.4 0.3 0.2 DDR 0.1 ...
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... IMD = -89.0dBFS -20 -40 -60 -80 -100 -120 0M 20M 40M 60M FREQUENCY (Hz) FIGURE 19. TWO-TONE SPECTRUM @ 70MHz 16 KAD5512HP All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° Conversion Rate (per speed grade). (Continued) 0 -20 -40 -60 -80 -100 -120 80M ...
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... Theory of Operation Functional Description The KAD5512HP is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 21). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges ...
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... OVDD the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512HP changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...
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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512HP is 500Ω. The SHA design uses a switched capacitor input stage (see Figure 41), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...
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... The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512HP is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... Peripheral Interface” on page 22. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. 21 KAD5512HP Data Format Output data can be presented in three formats: two’s complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4 ...
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... W0 CSB SCLK SDIO KAD5512HP Serial Peripheral Interface • • • • serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data input (SDI) and serial data input/output (SDIO). ...
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... CSB STALLING DATA WORD 1 FIGURE 38. N-BYTE TRANSFER protocol (described in the following). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the KAD5512HP functioning as a slave ...
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... Figures 37 and 38 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams. 24 KAD5512HP SPI Configuration ADDRESS 0X00: CHIP_PORT_CONFIG Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various microcontrollers ...
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... TABLE 8. COARSE GAIN ADJUSTMENT NOMINAL COARSE GAIN ADJUST 0x22[3:0] Bit3 Bit2 Bit1 Bit0 25 KAD5512HP TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER –Full Scale (0x00) Mid–Scale (0x80) +Full Scale (0xFF) Nominal Step Size ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to “ ...
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... ADDRESS 0X72: CLOCK_DIVIDE The KAD5512HP has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “Clock Input Considerations” on page 31). This functionality can be overridden and controlled through the SPI, as shown in Table 11 ...
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... Device Test The KAD5512HP can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 15) are set on the output bus on alternating clock phases ...
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... Output_Mode_A Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA other codes = reserved 74 Output_Mode_B 75 Config_Status 76-BF Reserved 28 KAD5512HP TABLE 16. SPI MEMORY MAP BIT 6 BIT 5 BIT 4 BIT 3 LSB Soft First Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # ...
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... AVDD CSAMP 1.6pF INP Φ Φ 1000O Ω CSAMP AVDD 1.6pF INN Φ Φ FIGURE 41. ANALOG INPUTS 29 KAD5512HP TABLE 16. SPI MEMORY MAP (Continued) BIT 6 BIT 5 BIT 4 BIT 3 [1: Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved Reserved B6 B5 ...
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... FIGURE 45. LVDS OUTPUTS 0.535V 72 Pin/48 Pin Package Options The KAD5512HP is available in both 72 pin and 48 pin packages. The 48 pin package option supports LVDS DDR only. A reduced set of pin selectable functions are available in the 48 pin package due to the reduced pinout; (OUTMODE, OUTFMT, and CLKDIV pins are not available). ...
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... Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. 31 KAD5512HP Definitions Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 KAD5512HP Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic ...
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... Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09 7.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 6.80 Sq 5.60 Sq TYPICAL RECOMMENDED LAND PATTERN 33 KAD5512HP Exp. DAP 7.00 5.60 Sq. 25 0.90 Max 44X 0.50 C 48X 0.25 48X 0.60 NOTES: 1 ...
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... Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 34 KAD5512HP 10. 72X 0.40 BOTTOM VIEW 0.90 Max 68X 0.50 72X 0. REF C 72X 0.60 NOTES: 1. Dimensions are in millimeters. ...