AD7328BRUZ Analog Devices Inc, AD7328BRUZ Datasheet - Page 28

• Manufacturer Part Number: AD7328BRUZ
• Description: IC ADC 12BIT+ SAR 8CHAN 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7328BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 30mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 1MSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7328CBZ - BOARD EVALUATION FOR AD7328
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

AD7328
MODES OF OPERATION
The AD7328 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7328 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE
(PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate perfor-
mance with the AD7328 being fully powered up at all times.
Figure 48 shows the general operation of the AD7328 in
normal mode.
The conversion is initiated on the falling edge of CS , and the track-
and-hold enters hold mode, as described in the
section. The data on the DIN line during the 16 SCLK transfer
is loaded into one of the on-chip registers if the write bit is set.
The register is selected by programming the register select bits
(see
DOUT
SCLK
DIN
CS
Table 8
SDATA
SCLK
PART IS IN FULL
SHUTDOWN
DIN
CS
).
1
3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2
1
Figure 48. Normal Mode
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
DATA INTO CONTROL REGISTER
REGISTER
PM1 = 0, PM0 = 0
INVALID DATA
Serial Interface
Figure 49. Exiting Full Shutdown Mode
16
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t
POWER-UP
The AD7328 remains fully powered up at the end of the con-
version if both PM1 and PM0 contain 0 in the control register.
To complete the conversion and access the conversion result
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, t
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7328 is powered
down. The part retains information in the registers during full
shutdown. The AD7328 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the control
register are changed.
A write to the control register with PM1 = PM0 = 1 places the
part into full shutdown mode. The AD7328 enters full shut-
down mode on the 15
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15
Figure 49 shows how the AD7328 is configured to exit full shut-
down mode. To ensure that the AD7328 is fully powered up,
t
THE PART IS FULLY POWERED UP
ONCE
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
POWER-UP
1
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
t
POWER-UP
should elapse before the next CS falling edge.
th
SCLK rising edge when the control register is updated.
DATA INTO CONTROL REGISTER
HAS ELAPSED
IN CONTROL REGISTER
th
SCLK rising edge when the control register
QUIET
, has elapsed.
16