AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 40

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

AD73322L
DAC TIMING CONTROL EXAMPLE
The AD73322L’s DAC is loaded from the DAC register contents
just before the ADC register contents are loaded to the serial
register (SDOFS going high). This default DAC load position
can be advanced in time to occur earlier with respect to the
SDOFS going high. Figure 50 shows an example of the ADC
unload and DAC load sequence. At time t
to indicate that a new ADC word is ready. Following the
SDOFS pulse, 16 bits of ADC data are clocked out on SDO in
the subsequent 16 SCLK cycles, finishing at time t
DSP’s SPORT has received the 16-bit word. The DSP may
process this information and generate a DAC word to be sent to
FROM DAC REGISTER
DATA REGISTER
DAC LOAD
UPDATE
SDOFS
SDIFS
SCLK
SDO
SDI
SE
t
1
1
, the SDOFS is raised
ADC WORD
2
where the
t
2
Figure 48. DAC Timing Control
Rev. A | Page 40 of 48
the AD73322L. Time t
sending the DAC word to the AD73322L. This sequence ends at
time t
the AD73322L’s serial register. However, the DAC is not
updated from the DAC register until time t
accept-able in certain applications. In order to reduce this delay
and load the DAC at time t
programmed with a suitable setting corresponding to the
required time advance (refer to Table 15 for details of DAC
timing control settings).
t
3
DAC WORD
4
, where the DAC register is updated from the 16 bits in
t
4
t
6
3
marks the beginning of the sequence of
6
, the DAC advance register can be
t
5
5
, which may not be