AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 16

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

AD73322L
In mixed control/data mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.
DECODER CHANNEL
The decoder channels consist of digital interpolators, digital
sigma-delta modulators, single bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain
amplifiers with differential outputs.
DAC CODING
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
INTERPOLATION FILTER
The anti-imaging interpolation filter is a sinc-cubed digital
filter that up-samples the 16-bit input words from the input
sample rate to a rate of DMCLK/8, while filtering to attenuate
images produced by the interpolation process. Its Z transform is
given as
where N is determined by the sampling rate
The DAC receives 16-bit samples from the host DSP processor
at the programmed sample rate of DMCLK/N. If the host
processor fails to write a new value to the serial port, the
existing (previous) data is read again. The data stream is filtered
by the anti-imaging interpolation filter, but there is an option to
bypass the interpolator for the minimum group delay
configuration by setting the IBYP bit (CRE:5) of Control
Register E. The interpolation filter has the same characteristics
as the ADC’s antialiasing decimation filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes the
signal so that errors inherent to the process are minimized in
the pass band of the converter. The bit-stream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
ANALOG SMOOTHING FILTER AND PGA
The output of the single bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms
part of the output programmable gain amplifier (PGA).
The PGA can be used to adjust the output signal level from
−15 dB to +6 dB in 3 dB steps, as shown in Table 9. The PGA
gain is set by bits OGS0, OGS1, and OGS2 (CRD:4-6) in
Control Register D.
[(1 − Z
(N = 32 @ 64 kHz . . . N = 256 @ 8 kHz)
−N
)/(1 − Z
−1
)]
3
Rev. A | Page 16 of 48
Table 9. PGA Settings for the Decoder Channel
OGS2
0
0
0
0
1
1
1
1
DIFFERENTIAL OUTPUT AMPLIFIERS
The decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal is
dc-biased to the codec’s on-chip voltage reference.
VOLTAGE REFERENCE
The AD73322L reference, REFCAP, is a band gap reference that
provides a low noise, temperature-compensated reference to the
DAC and ADC. A buffered version of the reference is also made
available on the REFOUT pin, and can be used to bias other
external analog circuitry. The reference has a default nominal
value of 1.2 V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
REFCAP
REFOUT
VOUTN1
VOUTP1
VFBN1
VFBP1
VINN1
VINP1
INVERTING
OP AMPS
V
REF
OGS1
0
0
1
1
0
0
1
1
Figure 18. Analog Input/Output Section
LOOP-BACK
ANALOG
+6/–15dB
SELECT
PGA
REFERENCE
OGS0
0
1
0
1
0
1
0
1
GAIN
CONTINUOUS
±1
LOW-PASS
FILTER
INVERT
TIME
Gain (dB)
+6
+3
0
−3
−6
−9
−12
−15
SINGLE-
ENABLE
GAIN TAP
ANALOG
AD73322L
ENDED
V
REF
0/38dB
PGA