AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 17

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

ANALOG AND DIGITAL GAIN TAPS
The AD73322L features analog and digital feedback paths
between input and output. The amount of feedback is deter-
mined by the gain setting which is programmed in the control
registers. This feature can typically be used for balancing the
effective impedance between input and output when used in
subscriber line interface circuit (SLIC) interfacing.
Analog Gain Tap
The analog gain tap is configured as a programmable
differential amplifier whose input is taken from the ADC’s
input signal path. The output of the analog gain tap is summed
with the output of the DAC. The gain is programmable using
Control Register F (CRF:0-4) to achieve a gain of −1 to +1 in
32 steps with muting being achieved through a separate control
setting (Control Register F Bit 7). The gain increment per step
is 0.0625. The AGT is enabled by powering-up the AGT control
bit in the power control register (CRC:1). When this bit is
set (=1), CRF becomes an AGT control register with CRF:0-4
holding the AGT coefficient, CRF:5 becomes an AGT enable
and CRF:7 becomes an AGT mute control bit.
REGISTER
CONTROL
RESET
SDIFS
1A
SDI
SE
8
EXTERNAL
DIVIDER
MCLK
MCLK
3
REGISTER
CONTROL
1B
REGISTER
REGISTER
CONTROL
CONTROL
DMCLK INTERNAL
8
SERIAL REGISTER 1
1G
1H
SERIAL PORT 1
16
REGISTER
CONTROL
(SPORT 1)
8
1C
REGISTER
CONTROL
1F
8
REGISTER
CONTROL
8
1D
DIVIDER
SCLK
2
CONTROL
REGISTER
8
Figure 19. SPORT Block Diagram
1E
SCLK
Rev. A | Page 17 of 48
SDOFS1
SDO1
REGISTER
CONTROL
SDIFS2
RESET
Control bit CRF:5 connects/disconnects the AGT output to the
summer block at the output of the DAC section while control
bit CRF:7 overrides the gain tap setting with a mute, (zero gain)
setting. Table 10 shows the gain vs. digital setting for the AGT.
In this table, AGT and DGT weights are given for the case of
VFBNx (connected to the sigma-delta modulator’s positive
input) being at a higher potential than VFBPx (connected to the
sigma-delta modulator’s negative input).
Table 10. Analog Gain Tap Settings
AGTC4
0
0
0
0
0
0
1
1
1
1
SDI2
2A
SE
8
EXTERNAL
DIVIDER
MCLK
MCLK
3
CONTROL
REGISTER
AGTC3
0
0
0
0
0
1
0
1
1
1
2B
REGISTER
REGISTER
CONTROL
CONTROL
DMCLK INTERNAL
8
SERIAL REGISTER 2
2G
2H
SERIAL PORT 2
16
REGISTER
CONTROL
(SPORT 1)
AGTC2
0
0
0
0
1
1
0
1
1
1
8
2C
REGISTER
CONTROL
2F
8
REGISTER
CONTROL
AGTC1
0
0
1
1
0
1
0
0
1
1
8
2D
DIVIDER
SCLK
2
CONTROL
REGISTER
0
1
0
1
AGTC0
0
1
0
1
0
1
8
2E
SCLK
SDOFS
AD73322L
SDO
Gain (dB)
1.00
0.9375
0.875
0.8125
0.75
0.0625
−0.0625
−0.875
−0.9375
−1.00