AD9878BST Analog Devices Inc, AD9878BST Datasheet - Page 28

• Manufacturer Part Number: AD9878BST
• Description: IC FRONT-END MIXED-SGNL 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9878BST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 4
• Power (watts): 673mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-LQFP

AD9878
Driving the Input
The IF ADCs have differential switched capacitor sample-and-
hold amplifier (SHA) inputs. The nominal differential input
impedance is 4.0 kΩ||3 pF. This impedance can be used as the
effective termination impedance when calculating filter transfer
characteristics and voltage signal attenuation from nonzero source
impedances. For best performance, additional requirements must
be met by the signal source. The SHA has input capacitors that
must be recharged each time the input is sampled. This results in
a dynamic input current at the device input, and demands that
the source has low (<50 Ω) output impedance at frequencies up
to the ADC sampling frequency. Also, the source must have
settling of better than 0.1% in less than half the ADC clock period.
Another consideration for getting the best performance from the
ADC inputs is the dc biasing of the input signal. Ideally, the signal
should be biased to a dc level equal to the midpoint of the ADC
reference voltages, REFT12 and REFB12. Nominally, this level is
1.2 V. When ac-coupled, the ADC inputs self-bias to this voltage
and require no additional input circuitry. Figure 35 illustrates a
recommended circuit that eases the burden on the signal source
by isolating its output from the ADC input. The 33 Ω series
termination resistors isolate the amplifier outputs from any
capacitive load, which typically improves settling time. The series
capacitors provide ac signal coupling, which ensures that the
ADC inputs operate at the optimal dc-bias voltage. The shunt
capacitor sources the dynamic currents required to charge the
SHA input capacitors, removing this requirement from the ADC
buffer. The values of C
determine the correct HPF and LPF corner frequencies.
V
Figure 35. Simple ADC Drive Configuration
S
33Ω
33Ω
C
and C
C
C
C
C
S
should be calculated to
C
S
AIN+
AIN–
Rev. A | Page 28 of 36
Receive Timing
The AD9878 sends multiplexed data to the IF10 and IF12 outputs
upon every rising edge of MCLK. RxSYNC frames the start of
each IF10 data symbol. The 10-bit and 12-bit ADCs are read
completely upon every second MCLK cycle. RxSYNC is high
for every second 10-bit ADC data if the 10-bit ADC is not in
power-down mode. The Rx timing diagram is shown in Figure 36.
IF10 DATA
IF12 DATA
IF10 DATA
REFCLK
RxSYNC
REFCLK
RxSYNC
IF DATA
Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC)
Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA)
MCLK
MCLK
t
t
MD
MD
IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]
IF12A
IF10[9:5]
IF12A OR IF12B
Figure 36. Rx Port Timing
IF10[4:0]
IF12B
t
IF12B
IF10[9:5]
t
EE
IF12A OR IF12B
EE
IF12B
IF10[4:0]
t
t
OD
OD
IF10[9:5] IF10[4:0]
IF10[9:5]
IF12A
IF12A OR IF12B
IF10[4:0]
M/N = 2
M/N = 2
IF12B