AD9878BST Analog Devices Inc, AD9878BST Datasheet - Page 27

• Manufacturer Part Number: AD9878BST
• Description: IC FRONT-END MIXED-SGNL 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9878BST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 4
• Power (watts): 673mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-LQFP

∑-∆ OUTPUTS
An on-chip ∑-∆ output provides a digital logic bit stream with
an average duty cycle that varies between 0% and (255/256)%,
depending on the programmed code, as shown in Figure 32.
This bit stream can be low-pass filtered to generate a
programmable dc voltage of
where:
In cable set-top box applications, the output can be used to
control external variable gain amplifiers or RF tuners. A
single-pole, RC, low-pass filter provides sufficient filtering
(see Figure 33). In more demanding applications, where
additional gain, level-shift, or drive capability is required,
consider using a first- or second-order filter (see Figure 34).
V
V
AD9878
H
L
=
=
V
0
V
DC
MCLK
4 .
DRVDD
V
=
SIGMA-DELTA
[
(
Figure 34. ∑-∆ Active Filter with Gain and Offset
AD9878
∑
CONTROL
FFh
Σ-∆
00h
01h
02h
80h
−
-
WORD
∆
0
÷8
6 .
Code
8 t
Figure 32. ∑-∆ Output Signals
V
8 t
V
MCLK
SD
Figure 33. ∑-∆ RC Filter
MCLK
TYPICAL: R = 50kΩ
256
8
V
TYPICAL: R = 50kΩ
)
R
OUT
×
C
256 × 8 t
V
256 × 8 t
C = 0.01µF
f
= (V
–3dB
DAC
H
Σ-∆
V
]
R1
OFFSET
SD
+
C = 0.01µF
f
= 1/(2πRC) = 318Hz
–3dB
MCLK
V
+ V
MCLK
R
L
OFFSET
= 1/(2πRC) = 318Hz
C
R
OP250
) (1 + R/R1)/2
R
C
V
OUT
DC (V
L
TO V
Rev. A | Page 27 of 36
H
)
RECEIVE PATH (Rx)
The AD9878 includes three high speed, high performance ADCs.
The 10-bit and dual 12-bit direct-IF ADCs deliver excellent under-
sampling performance with input frequencies as high as 70 MHz.
The sampling rate can be as high as 29 MSPS. The ADC sampling
frequency can be derived directly from the OSCIN signal, or from
the on-chip OSCIN multiplier. For highest dynamic performance,
choose an OSCIN frequency that can be directly used as the
ADC sampling clock. Digital 12-bit ADC outputs are multiplexed
to one 12-bit bus, clocked by a frequency (f
sampling rate. The IF ADCs use a multiplexer to a 12-bit interface
with an output word rate of f
IF10 AND IF12 ADC OPERATION
The IF10 and IF12 ADCs have a common architecture and
share several characteristics from an applications standpoint.
Most of the information in the following section is applicable to
both IF ADCs; differences, where they exist, are highlighted.
Input Signal Range and Digital Output Codes
The IF ADCs have differential analog inputs labeled IF+ and IF−.
The signal input, V
input pins, V
determined by the internal reference voltages, REFT and REFB,
which define the top and bottom of the scale. The peak input
voltage to the ADC is the difference between REFT and REFB,
which is 1 V p-p. This results in an ADC full-scale input voltage
of 2 V
shown in Table 11.
Table 11. Digital Output Codes
IF12[11:0]
111…111
111…111
111…110
…
100…001
100…000
011…111
…
000…001
000…000
000…000
PPD
. The digital output codes are straight binary and are
AIN
= V
AIN
IF+
, is the voltage difference between the two
− V
Input Signal Voltage
V
V
V
…
V
V
V
…
V
V
V
AIN
AIN
AIN
AIN
AIN
AIN
AIN
AIN
AIN
IF−
≥ +1.0 V
= +1.0 V − 1 LSB
= +1.0 V − 2 LSB
= 0 V + 1 LSB
= 0.0 V
= 0 V − 1 LSB
= −1.0 V + 2 LSB
= −1.0 V
< −1.0 V
. The full-scale input voltage range is
MCLK
.
MCLK
) four times the
AD9878