AD9878BST Analog Devices Inc, AD9878BST Datasheet - Page 20

• Manufacturer Part Number: AD9878BST
• Description: IC FRONT-END MIXED-SGNL 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9878BST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 4
• Power (watts): 673mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-LQFP

AD9878
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 23, a
block diagram of the device architecture. The device consists of a
transmit path, receive path, and auxiliary functions, such as a PLL,
a ∑-∆ DAC, a serial control port, and a cable amplifier interface.
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit
current output DAC.
The receive path contains a 10-bit ADC and dual 12-bit ADCs.
All internally required clocks and an output system clock are
generated by the PLL from a single crystal or clock input.
IF12[11:0]
CA PORT
TxIQ[5:0]
PROFILE
IF10[4:0]
REFCLK
RxSYNC
TxSYNC
MCLK
SDIO
12
6
3
4
5
ASSEMBLER
Q
DATA
I
INTERFACE
INTERFACE
Rx PORT
PROFILE
SELECT
SERIAL
CA
12
12
IF10
IF12
÷R
(
f
IQCLK
AD9878
FIR LPF
)
4
4
÷4
12
12
5
12
(
f
MCLK
CIC LPF
MUX
MUX
)
4
4
Figure 23. AD9878 Block Diagram
÷4
Rev. A | Page 20 of 36
CLAMP LEVEL
QUADRATURE
÷8
÷2
÷2
MODULATOR
DDS
(
(
f
f
OSCIN
OSCIN
COS
SIN
)
)
The 12-bit and 10-bit IF ADCs can convert direct IF inputs of
up to 70 MHz and run at sample rates of up to 29 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9878 to process an NTSC and a QAM
channel simultaneously.
The programmable ∑-∆ DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage-
controlled tuners. The CA port provides an interface to the
AD832x family of programmable gain amplifier (PGA) cable
drivers, enabling host processor control via the MxFE serial
port (SPORT).
–
SINC
BYPASS
DAC GAIN CONTROL
SINC
+
12
12
–1
10
(
–1
f
SYSCLK
Σ-∆ INPUT
ADC
ADC
MUX
)
12
ADC
OSCIN × M
PLL
8
FLAG0
DAC
DAC
MUX
MUX
Σ-∆
(
f
OSCIN
)
Tx OUTPUT
IF12B INPUT
FSADJ
XTAL
FLAG[2:1]
IF10 INPUT
OSCIN
VIDEO IN
IF12A INPUT
Σ-∆ OUTPUT