AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 4

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

AD9879
SPECIFICATIONS
Table 1.
Parameter
OSCIN AND XTAL CHARACTERISTICS
Tx DAC CHARACTERISTICS
Tx MODULATOR CHARACTERISTICS
Tx GAIN CONTROL
IQ ADC CHARACTERISTICS
V
R
Frequency Range
Duty Cycle
Input Impedance
MCLK Cycle to Cycle Jitter
Resolution
Maximum Sample Rate
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz
Output Voltage Compliance Range
Wideband SFDR
Narrow-band SFDR (±1 MHz Window)
I/Q Offset
Pass-Band Amplitude Ripple (f < f
Pass-Band Amplitude Ripple (f < f
Stop-Band Response (f > f
Gain Step Size
Gain Step Error
Settling Time to 1% (Full-Scale Step)
Resolution
Maximum Conversion Rate
Pipeline Delay
Offset Matching Between I and Q ADCs
Gain Matching Between I and Q ADCs
Analog Input
AC Performance (A
SET
AS
Crystal and OSCIN Multiplier Enabled at 16×
5 MHz Analog Out, I
65 MHz Analog Out, I
5 MHz Analog Out, I
Input Voltage Range
Input Capacitance
Differential Input Resistance
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
= 3.3 V ± 5%, V
= 4.02 kΩ, 75 Ω DAC load, unless otherwise noted.
1
IN
DS
= 0.5 dBFS, f
OUT
OUT
= 3.3 V ± 10%, f
1
OUT
= 10 mA
= 10 mA
IQCLK
= 10 mA
× 3/4)
IN
IQCLK
IQCLK
= 5 MHz)
/8)
/4)
OSCIN
= 27 MHz, f
Temp
Full
Full
25°C
25°C
N/A
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
N/A
Full
N/A
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
SYSCLK
Rev. A | Page 4 of 32
Test Level
II
II
III
III
N/A
II
II
I
I
I
III
III
III
III
II
III
III
III
II
II
II
II
III
III
III
N/A
II
N/A
III
III
III
III
III
I
I
I
I
= 216 MHz, f
Min
3
35
232
4
−2.0
1.18
−0.5
60.8
44.0
65.4
50
14.5
5.00
34.7
41.3
MCLK
= 54 MHz (M = 8), ADC clock from OSCIN,
Typ
50
100||3
6
12
10
−1.0
±1.0
1.23
±2.5
±8
5
−110
66.9
46.2
72.3
55
0.5
<0.05
1.8
6
3.5
±4.0
±2.0
1
2.0
4
5.8
36.5
−50
51
Max
29
65
20
+2.0
1.28
+1.5
±0.1
±0.5
−63
−36.2
Unit
MHz
%
MΩ||pF
ps rms
Bits
MHz
mA
% FS
% FS
V
LSB
LSB
pF
dBc/Hz
V
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
µs
Bits
MHz
ADC cycles
LSBs
LSBs
Vppd
pF
kΩ
Bits
dB
dB
dB